没有合适的资源？快使用搜索试试~ 我知道了~

文库首页开发技术其它Transactional Memory - CS4021 - Slides-计算机科学

Transactional Memory - CS4021 - Slides-计算机科学

Papers

Specs

Decks

Manuals

0 下载量 51 浏览量 2021-04-22 18:18:28 上传评论收藏 484KB PDF 举报

温馨提示

试读

29页

HARDWARE TRANSACTIONAL MEMORYCS4021/4521 :copyright: 2017 jones@tcd.ie School of Computer Science and Statistics, Trinity College Dublin 24-Nov-17 1Hardware Transactional Memory• transactions normally associated with databases• in this context, think of a transaction as the atomic update of a number of memory locations [eg. atomic update of a data structure]• a transaction is a finite sequence of machine instructions that read and write memory locations, executed by a single thread, satisfying t

资源推荐

资源详情

资源评论

《Transactional Memory》这本书是关于计算机架构合成讲座系列的一部分，由James R. Larus和Ravi Rajwar撰写，于2007年出版。这本书深入探讨了事务性内存（Transactional Memory，简称TM）这一关键的计算机系统设计...

HARDWARE TRANSACTIONAL MEMORY

Hardware Transactional Memory

• transactions normally associated with databases

• in this context, think of a transaction as the atomic update of a number of memory

locations [eg. atomic update of a data structure]

• a transaction is a finite sequence of machine instructions that read and write

memory locations, executed by a single thread, satisfying the following properties:

• serializability: transactions appear to execute serially, meaning that the steps of

one transaction never appear to be interleaved with the steps of another

• committed transactions are never observed by different threads to execute in

different orders

• atomicity: each transaction makes a sequence of tentative changes [NOT visible

to other threads] to memory and the architectural state [CPU registers] and

then either

 COMMITS - making its tentative changes visible to other threads

 ABORTS - causing its tentative changes to be discarded

HARDWARE TRANSACTIONAL MEMORY

Hardware Transactional Memory

• Transactional Memory: Architectural Support of Lock-Free Data Structures

Maurice Herlihy and J. Eliot B. Moss

Proceedings of the 20th Annual International Symposium on Computer Architecture

1993

• motivations

 lock free operations on a data structure will not be prevented if other threads stall

mid execution

 avoids common problems with mutual exclusion

 out performs best known locking techniques

• takes advantage of the first level cache and the cache coherency protocol

• tentative changes made to the first level cache [and architectural state] ONLY

• tentative changes made visible atomically on a successful commit

HARDWARE TRANSACTIONAL MEMORY

Hardware Transactional Memory

• typical transactional code

• will describe Intel Transactional Synchronization eXtension [TSX]

• implemented 20 years after original Herlihy and Moss paper

• support for hardware lock elision [HLE] and restricted transactional memory [RTM]

• first Haswell CPU with TSX released Jun-13 [Aug-14 bug reported in first implementation]

• NOT all later CPUs support TSX [need to test CPUID.07H.EBX.RTM [bit 11] = 1]

start transaction start transaction

< UPDATE SHARED DATA STRUCTURE > < UPDATE SHARED DATA STRUCTURE >

commit transaction commit transaction

retry on failure retry on failure

HARDWARE TRANSACTIONAL MEMORY

Intel TSX

• 4 new assembly language instructions for RTM

 xbegin transaction begin

 xend transaction end

 xabort transaction abort

 xtest test if in a transaction

• example transactional code [IA32/x64 assembly language]

xbegin L0

< INSTRUCTIONS TO UPDATE SHARED DATA STRUCTURE >

xend

< HERE ON SUCCESSFUL COMMIT >

L0: < HERE ON ABORT > [eax contains RTM abort status]

• eager conflict detection

• transaction fails as soon as a conflict is detected

HARDWARE TRANSACTIONAL MEMORY

Intel RTM

• why does a transaction abort?

• instructions inside a transaction read and write memory locations

• transaction read set and write set

• transaction will abort if any other CPU...

 reads a location in its write set

 writes to a location in its read or write set

• transactions may also abort due to hardware limitations, context switches, interrupts,

page faults, update of PTE Accessed and Dirty bits, ...

• MUST provide a non transactional execution path that can be executed if a

transaction fails continuously

剩余28页未读，继续阅读

评论收藏

内容反馈

资源评论

资源反馈

评论星级较低，若资源使用遇到问题可联系上传者，3个工作日内问题未解决可申请退款~

weixin_38691194

粉丝: 5
资源: 910

上传资源快速赚钱

我的内容管理展开

我的资源快来上传第一个资源

我的收益

登录查看自己的收益

我的积分登录查看自己的积分

我的C币登录后查看C币余额

我的收藏

我的下载

下载帮助

前往需求广场，查看用户热搜

Transactional Memory - CS4021 - Slides-计算机科学

Transactional Memory

slides

ScienceSlides

transactional-memory-simulator

transactional-memory-synthesis-lectures-on-computer-architecture.pdf

The Transactional Memory - Garbage Collection Analogy (analogy_oopsla07)-计算机科学

Principles of Transactional Memory

Chihuahua - A Concurrent, Moving, Garbage Collector using Transactional Memory - 2015 (anderson-transact-2015)-计算机科学

Investigation of Hardware Transactional Memory - 2015 (Andrew-Nguyen-Thesis)-计算机科学

Software Transactional Memory - Why Is It Only a Research Toy (p46-cascaval)-计算机科学

typeorm-transactional-cls-hooked:用于typeorm的事务方法装饰器，使用cls-hooked处理和传播不同存储库和服务方法之间的事务。 由Spring Trasnactional注释和CLS序列化表示

Hardware Transactional Memory on Haswell-计算机科学

事务内存（Transactional Memory）

Resoling transactional Access-Analytic Performance Trade_offs

PyPI 官网下载 | mailchimp_transactional-1.0.9-py3-none-any.whl

PyPI 官网下载 | mailchimp_transactional-1.0.40-py3-none-any.whl

PyPI 官网下载 | mailchimp_transactional-1.0.18-py3-none-any.whl

Transactional Memory.rar

spring-@Transactional-jar

Software-Transactional-Memory.pptx

Laravel开发-transactional-soft-deletes

High-Performance Hardware Transactional Memory Systems.pdf

Programming-Persistent-Memory-2020.pdf

Parallel Programming with Transactional Memory (p38-drepper)-计算机科学

Qt 5实现串口调试助手 （源工程文件、0积分下载）

【SystemVerilog】路科验证V2学习笔记（全600页）.pdf

最新资源

typeorm-transactional-cls-hooked:用于typeorm的事务方法装饰器，使用cls-hooked处理和传播不同存储库和服务方法之间的事务。由Spring Trasnactional注释和CLS序列化表示

Qt 5实现串口调试助手（源工程文件、0积分下载）