带有部分轻掺杂柱的高压超结横向双扩散金属氧化物半导体
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Chin. Phys. B Vol. 22, No. 6 (2013) 068501
High-voltage super-junction lateral double-diffused metal oxide
semiconductor with a partial lightly doped pillar
∗
Wu Wei(伍 伟)
†
, Zhang Bo(张 波), Fang Jian(方 健),
Luo Xiao-Rong(罗小蓉), and Li Zhao-Ji(李肇基)
State Key Laboratory of Electronic Thin Films and Integrated Devices,
University of Electronic Science and Technology of China, Chengdu 610054, China
(Received 13 September 2012; revised manuscript received 15 December 2012)
A novel super-junction lateral double-diffused metal–oxide semiconductor (SJ-LDMOS) with a partial lightly doped
P pillar (PD) is proposed. Firstly, the reduction in the partial P pillar charges ensures the charge balance and suppresses
the substrate-assisted depletion effect. Secondly, the new electric field peak produced by the P/P
−
junction modulates the
surface electric field distribution. Both of these result in a high breakdown voltage (BV). In addition, due to the same
conduction paths, the specific on-resistance (R
on,sp
) of the PD SJ-LDMOS is approximately identical to the conventional
SJ-LDMOS. Simulation results indicate that the average value of the surface lateral electric field of the PD SJ-LDMOS
reaches 20 V/µm at a 15 µm drift length, resulting in a BV of 300 V.
Keywords: super-junction, lateral double-diffused metal–oxide semiconductor, partial lightly doped pillar,
electric field modulation, breakdown voltage
PACS: 85.30.De, 85.30.Tv, 84.70.p DOI: 10.1088/1674-1056/22/6/068501
1. Introduction
With the development of smart power-integrated cir-
cuits (SPICs), the demand for power devices that can be
easily integrated into SPICs has been increasing more and
more. For a commonly used integrated device, the lateral
double-diffusion metal–oxide semiconductor field-effect tran-
sistor (MOSFET)/(LDMOS) acts as an important constituent
in power electronics applications. The super-junction (SJ)
concept
[1]
used in the LDMOS
[2,3]
improves the tradeoff char-
acteristics between the breakdown voltage and the specific on-
resistance (R
on,sp
). Unfortunately, the N pillars of the conven-
tional SJ-LDMOST are depleted by neighboring P pillars as
well as by the P substrate, while the P pillars are depleted by
neighboring N pillars only. This is called the substrate-assisted
depletion effect. This effect causes a charge imbalance and re-
sults in the decrease of the breakdown voltage (BV). To elim-
inate it, several new structures have been reported.
[4–13]
In this paper, an SJ-LDMOS with partial lightly doped P
pillar (PD) is proposed to suppress the substrate-assisted de-
pletion effect. Owing to the decrease in the charges in the P
pillar, the charge balance is achieved and the new peak appear-
ing at the P/P
−
junction modulates the surface electric field
distribution. Thus, a higher BV is obtained according to the
simulation results.
2. Device structure and mechanism
The proposed PD SJ-LDMOS is illustrated in Fig. 1. The
key feature of the device is that the P pillar in the SJ region is
split into two distinct parts. The first one is the heavily doped P
pillar, of which the doping concentration is equal to that of the
N pillar. The second is the lightly doped P pillar with a doping
concentration of N
P
and a length L
P
. The cross section along
the AA
0
plane is shown in Fig. 2. On the one hand, the use
of the lightly doped P pillar causes a reduction in the p-type
charge density, thereby ensuring the charge balance among
the N pillar, the P pillar, and the P substrate. The substrate-
assisted depletion effect therefore can be suppressed. On the
other hand, the electric field peak which occurs at the P/P
−
junction modulates the electric field distribution in the N pil-
lar, which causes a uniform distribution of the surface electric
field.
Three-dimensional (3D) device simulations are carried
out by Sentaurus
[14]
in order to demonstrate the performance
of the PD SJ-LDMOS. The PD SJ-LDMOS is compared with
the conventional SJ-LDMOS, and the relevant device parame-
ters are listed in Table 1.
N
+
N
+
P-body
source
gate
drain
P substrate (ρ
sub
)
x
y
z
N
P
N
P
N
P
N pillar
h
P
-
P
+
A
A’
B’
B
N(N
D
)
P(N
A
)
P
-
(N
P
)
L
D
Fig. 1. Three-dimensional (3D) view of the PD SJ-LDMOS.
∗
Project supported by the National Science and Technology Major Project of the Ministry of Science and Technology of China (Grant No. 2010ZX02201), the
National Natural Science Foundation of China (Grant No. 61176069), and the National Defense Pre-Research of China (Grant No. 51308020304).
†
Corresponding author. E-mail: wuweiwwu@163.com
© 2013 Chinese Physical Society and IOP Publishing Ltd http://iopscience.iop.org/cpb http://cpb.iphy.ac.cn
068501-1
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