High-performance top-gated monolayer SnS
2
field-
effect transistors and their integrated logic circuits†
H. S. Song,
ab
S. L. Li,
*
b
L. Gao,
a
Y. Xu,
b
K. Ueno,
c
J. Tang,
*
a
Y. B. Cheng
ad
and K. Tsukagoshi
*
b
Two-dimensional (2D) layered semiconductors are very promising for post-silicon ultrathin channels and
flexible electronics due to the remarkable dimensional and mechanical properties. Besides molybdenum
disulfide (MoS
2
), the first recognized 2D semiconductor, it is also important to explore the wide
spectrum of layered metal chalcogenides (LMCs) and to identify possible compounds with high
performance. Here we report the fabrication of high-performance top-gated field-effect transistors
(FETs) and related logic gates from monolayer tin disulfide (SnS
2
), a non-transition metal
dichalcogenide. The measured carrier mobility of our monolayer devices reaches 50 cm
2
V
1
s
1
, much
higher than that of the back-gated counterparts (1cm
2
V
1
s
1
). Based on a direct-coupled FET logic
technique, advanced Boolean logic gates and operations are also implemented, with a voltage gain of
3.5 and output swing of >90% for the NOT and NOR gates, respectively. The superior electrical and
integration properties make monolayer SnS
2
a strong candidate for next-generation atomic electronics.
Introduction
Two dimensional (2D) materials
1
have attracted great attention
for next-generation ultra-thin-body electronics, optoelectronics
and exible devices due to their unique geometric structure and
physical properties. In the semiconductor industry, the atomic-
scale thickness and atness offer better electrostatic control
and scaling down ability than bulk materials,
2
which allows
considerably shorter gate, full depleted channel and relieved
requirement on dielectric thickness and, eventually, realizing
compact and high-speed integration circuits.
3
Besides, the
excellent mechanical properties and high crystallinity pave the
way for high-performance bendable electronic and optoelec-
tronic devices, as compared with conventional organic and
amorphous materials.
4
For electronic applications, the main
drawback of graphene
5
and derivatives
6–9
(the rst-generation
2D materials) is the lack of a sizable band gap and a large
switching ratio, which disables viable logic operations. It is thus
of great interest to nd semiconductors with not only an
appropriate band gap but also the extraordinary electrical and
mechanical properties. In this context, the layered metal chal-
cogenides (LMCs) have emerged as strong candidates that
satisfy the requirements of both semiconductivity and dimen-
sionality.
10–13
For example, mono- and few-layer MoS
2
devices
are successfully implemented in eld-effect transistors (FETs),
14
logic circuits
15
and show superior performances as compared
with graphene counterparts in current switching ratio and
standby power dissipation. On the other hand, the LMC family
covers a wide spectrum of compounds and it is also important
to identify other candidates possibly possessing superior elec-
trical properties to MoS
2
.
Tin disulde (SnS
2
) has a layered CdI
2
-type structure, in
which the Sn atoms are sandwiched by two layers of hexagonally
packed S atoms, and shows a bulk band gap 2.35 eV,
16
wider
than that of MoS
2
(1.2 eV). It is well known that a large band
gap is crucial in suppressing source to drain tunneling in short-
channel FETs in the aggressively integrated circuits nowadays.
15
Although much work has been done for SnS
2
or SnS
2
/graphene
composites in lithium ion batteries,
17–19
gas sensing,
20
eld
effect emission,
21
water splitting,
22
etc., there are few reports to
probe the electrical properties and integration based on
monolayer SnS
2
akes. Recently, Peng et al.
12
fabricated
conventional SiO
2
back-gated SnS
2
FETs, but only a low carrier
mobility of 1 cm
2
V
1
s
1
is observed in the back-gated geom-
etry, as compared to top-gated monolayer MoS
2
devices (15–55
cm
2
V
1
s
1
)
23
covered by high-k dielectrics. In this work, we
fabricated high-performance top-gated monolayer SnS
2
FETs
and related logic gates. The measured carrier mobility of our
a
Wuhan National Laboratory for Optoelectronics (WNLO) and School of Optical and
Electronic Information, Huazho ng University of Science and Technology (HUST),
Wuhan 430074, P. R. China. E-mail: jtang@mail.hust.edu.cn; li.songlin@nims.go.jp;
Tsukagoshi.Kazuhito@ nims.go.jp
b
International Center for Materials Nanoarchitectonics (WPI-MANA), National
Institute for Materials Science (NIMS), Tsukuba, Ibaraki 305-0044, Japan
c
Department of Chemistry, Graduate School of Science and Engineering, Saitama
University, Saitama 338-8570, Japan
d
Department of Materials Engineering, Monash University, Melbourne, Victoria, 3800,
Australia
† Electronic supplementary information (ESI) available. See DOI:
10.1039/c3nr01899g
Cite this: Nanoscale, 2013, 5, 9666
Received 18th April 2013
Accepted 29th July 2013
DOI: 10.1039/c3nr01899g
www.rsc.org/nanoscale
9666 | Nanoscale, 2013, 5, 9666–9670 This journal is ª The Royal Society of Chemistry 2013
Nanoscale
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