ADIADSP-BF609Blackfin处理器低成本评估方案资源-CSDN文库

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ADI ADSP-BF609 Blackfin处理器低成本评估方案处理器低成本评估方案

ADI公司的ADSP-BF609Blackfin处理器采用ADI/Intel微信号架构(MSA),具有正交RISC类微处理器指令集,单指令

多数据(SIMD)多媒体功能,处理器工作频率高达500MHz,静态功耗低,主要用在汽车电子,嵌入式工业控制,马达控

制,仪器仪表等.ADI公司的ADSP－BF609EZ－KITLite评估系统和CrossCoreEmbeddedStudio(CCES)开发工具

连接,用来评估ADSP－BF60xBlackfin处理器的功能.本文介绍了ADSP-BF609主要特性,方框图,Blackfin处理器核

框图,A

ADI公司的

ADSP-BF609 Evaluation Hardware for the ADSP-BF60x Blackfin Processor Family

The ADSP-BF609 processor is a member of the Blackfin family of products, incorporating the Analog Devices/Intel Micro

Signal Architecture (MSA). Blackfin processors combine a dual-MAC state-of-the-art signal processing engine, the

advantages of a clean, orthogonal RISC-like microprocessor instruction set, and single-instruction, multiple-data (SIMD)

multimedia capabilities into a single instruction-set architecture.

The processor offers performance up to 500 MHz, as well as low static power consumption. Produced with a low-power and

low voltage design methodology, they provide world-class power management and performance.

By integrating a rich set of industry-leading system peripherals and memory , Blackfin processors are the platform of choice

for next-generation applications that require RISC-like programmability, multimedia support, and leadingedge signal

processing in one integrated package. These applications span a wide array of markets, from automotive systems to

embedded industrial, instrumentation and power/motor control Applications.

ADSP-BF609 主要特性:

Dual-core symmetric high-performance Blackfin processor, up to 500 MHz per core

Each core contains two 16-bit MACs, two 40-bit ALUs, and a 40-bit barrel shifter

RISC-like register and instruction model for ease of programming and compiler-friendly support

Advanced debug, trace, and performance monitoring

Pipelined Vision Processor provides hardware to process signal and image algorithms used for pre- and co-processing of

video frames in ADAS or other video processing applications

Accepts a range of supply voltages for I/O operation.

Off-chip voltage regulator interface

349-ball (19 mm × 19 mm) RoHS compliant BGA package

存储器特性:

Each core contains 148K bytes of L1 SRAM memory (processor core-accessible) with multi-parity bit protection

Up to 256K bytes of L2 SRAM memory with ECC protection

Dynamic memory controller provides 16-bit interface to a single bank of DDR2 or LPDDR DRAM devices

Static memory controller with asynchronous memory interface that supports 8-bit and 16-bit memories

Flexible booting options from flash, eMMC and SPI memories and from SPI, link port and UART hosts

Memory management unit provides memory protection

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