Design of a Hybrid Reconfigurable Coprocessor
Xiang Wang
1
,Su Zhang
1
*, Wei Ni
1
, Yukun Song
1
, Yanhui Yang
2
, Jichun Bu
2
1
Institute of VLSI Design, Hefei University of Technology, Hefei, 230009, China
2
LZeal Information Technology Co., Ltd, Wuxi, 214072, China
* Email: zhangsu@hfut.edu.cn
Abstract
Reconfigurable processors are noticeable for their flexi-
bility and high computation performance. Combining a
general purpose processor with a reconfigurable copro-
cessor can improve the overall system performance. As
wide range of algorithms have appeared due to the in-
creasing complexity of applications, the general purpose
processors undertake more serial computing tasks, which
also leads to more time consumption during the task
switching. Meanwhile, higher bandwidth demand comes
with the increasing of computation efficiency. A hybrid
reconfigurable coprocessor has been proposed here,
which reduces its dependence on the general purpose
processor. Optimized L2-cache has been designed to
enhance the data locality and reusability. The proposed
coprocessor based on an FPGA has been implemented
which can operate at 100MHz. Experimental results
show that much better performance has been achieved
with this proposed coprocessor.
1. Introduction
Reconfigurable technology can obviously improve the
processing and computing ability without losing the
flexibility of general purposed processor (GPP), so it is
widely uesd in the area of high-performance computing
[1]. Typical SoC system is composed by GPP and pe-
ripherals and the execution efficiency of key algorithms
restrict the performance of the whole system, while the
performance of GPP usually cannot meet the demand of
applications. One of the solutions is Application Specific
Integrated Circuit (ASIC), but it aims at specific algo-
rithms with less flexibility.
Reconfigurable computing system is another solution
emerged in recent years [2][3], which contains reconfig-
urable coprocessors into SoC. In normal reconfigurable
computing systems, parallel and intensive tasks are usu-
ally performed by the reconfigurable coprocessor and the
serial or control tasks, e.g. loops and branch instructions
are allocated to GPP in order to improve the utilization
ratio of the reconfigurable coprocessor, which produces
more time consumption in the task switching between
the GPP and the reconfigurable coprocessor. Meanwhile,
great demand of bandwidth [1] comes with the high per-
formance of the reconfigurable coprocessor. In computa-
tion-intensive cases, data transmission between copro-
cessors and external
memory increase tremendously
and
sometimes coprocessors wait for new operation data,
which lead to processor starvation phenomenon [4].
In order to overcome the above shortcomings, a hybrid
reconfigurable coprocessor (RCCP) has been proposed
here, which contains two standalone computing units, a
reconfigurable array computing unit to perform parallel
intensive algorithms and a pipeline computing unit used
for serial and control operation. They can cooperate in
different modes to ensure that both of them could have
good utilization ratios. An optimized L2-cache with mul-
ti-channel has also been designed to tightly couple the
two computing units and effectively enhance the data
locality and reusability. With benefit from these im-
provements, RCCP features the efficient parallel compu-
ting ability and flexibility to perform complex and inten-
sive algorithms.
2. Architecture of RCCP
As shown in Fig. 1, RCCP mainly includes a reconfigu-
rable array computing unit, a pipeline computing unit,
global control unit, L2-cache and corresponding inter-
faces. Some components are introduced in the following:
Figure 1. Top level architecture of RCCP
978-1-4673-6417-1/13/$31.00 ©2013 IEEE
资源评论
