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Towards Write-Activity-Aware Page Table Management for

Non-volatile Main Memories

TIANZHENG WANG, University of Toronto

DUO LIU, Chongqing University and Key Laboratory of Dependable Service Computing in Cyber

Physical Society (Chongqing University), Ministry of Education of P. R. China

YI WANG and ZILI SHAO, Embedded Systems and CPS Lab, The Hong Kong Polytechnic University

Non-volatile memories such as phase change memory (PCM) and memristor are being actively studied

as an alternative to DRAM-based main memory in embedded systems because of their properties, which

include low power consumption and high density. Though PCM is one of the most promising candidates with

commercial products available, its adoption has been greatly compromised by limited write endurance. As

main memory is one of the most heavily accessed components, it is critical to prolong the lifetime of PCM.

In this article, we present write-activity-aware page table management (WAPTM), a simple yet effec-

tive page table management scheme for reducing unnecessary writes, by redesigning system software and

exploiting write-activity-aware features provided by the hardware. We implemented WAPTM in Google An-

droid based on the ARM architecture and evaluated it with real Android applications. Experimental results

show that WAPTM can signiﬁcantly reduce writes in page tables, proving the feasibility and potential of

prolonging the lifetime of PCM-based main memory through reducing writes at the OS level.

Categories and Subject Descriptors: D.4.2 [Operating Systems]: Storage Management—Main

memory; D.4.2 [Operating Systems]: Storage Management—Virtual memory; D.4.2 [Operating Sys-

tems]: Storage Management—Storage hierarchies; D.4.2 [Operating Systems]: Storage Management—

Allocation/deallocation strategies

General Terms: Design, Algorithms, Performance

Additional Key Words and Phrases: P hase change memory, non-volatile memory, memory management,

write activity aware, operating systems

An earlier version of this article has been published in Proceedings of the 17th ACM/IEEE Asia and South

Paciﬁc Design Automation Conference (ASP-DAC’12).

This work is partially supported by grants from the Research Grants Council of Hong Kong (GRF

152138/14E), the Innovation and Technology Support Programme of Innovation and Technology Fund of

Hong Kong (ITS/082/10), Germany/Hong Kong Joint Research Scheme sponsored by the Research Grants

Council of Hong Kong and the Germany Academic Exchange Service of Germany (G_HK021/12), The Hong

Kong Polytechnic University (4-ZZD7, G-YK24, G-YM10, and G-YN36), National Natural Science Founda-

tion of China (61272103, 61373049, and 61309004), National 863 Program (2013AA013202), Research Fund

for the Doctoral Program of Higher Education of China (20130191120030), Chongqing (cstc2012ggC40005

and cstc2013jcyjA40025), and Fundamental Research Funds for Central Universities (CDJZR14185501).

Duo Liu is the corresponding author.

Authors’ addresses: T. Wang, Department of Computer Science, University of Toronto, 10 King’s College Road,

Rm. 3302, Toronto, Ontario, Canada M5S 3G4; email: tzwang@cs.toronto.edu; D. Liu, College of Computer

Science, Chongqing University, 174 Shazheng Street, Chongqing, China 400044; email: liuduo@cqu.edu.cn;

Y. Wang, College of Computer Science and Software Engineering, Shenzhen University, Shenzhen, China

518060; email: yiwang@szu.edu.cn; Z. Shao, Department of Computing, The Hong Kong Polytechnic Univer-

sity, Hung Hom, Ko wloon, Hong Kong; email: cszlshao@comp.polyu.edu.hk.

Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted

without fee provided that copies are not made or distributed for proﬁt or commercial advantage and that

copies show this notice on the ﬁrst page or initial screen of a display along with the full citation. Copyrights for

components of this work owned by others than ACM must be honored. Abstracting with credit is permitted.

To copy otherwise, to republish, to post on servers, to redistribute to lists, or to use any component of this

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Publications Dept., ACM, Inc., 2 Penn Plaza, Suite 701, New York, NY 10121-0701 USA, fax +1 (212)

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 2015 ACM 1539-9087/2015/02-ART34 $15.00

DOI: http://dx.doi.org.10.1145/2697394

ACM Transactions on Embedded Computing Systems, Vol. 14, No. 2, Article 34, Publication date: February 2015.

34:2 T. Wang et al.

ACM Reference Format:

Tianzheng Wang, Duo Liu, Yi Wang, and Zili Shao. 2015. Towards write-activity-aware page table manage-

ment for non-volatile main memories. ACM Trans. Embedd. Comput. Syst. 14, 2, Article 34 (February 2015),

23 pages.

DOI: http://dx.doi.org.10.1145/2697394

1. INTRODUCTION

DRAM-based main memory is reaching its limit in many aspects, such as power con-

sumption and scalability. Replacing it with non-volatile memories, such as memristor

[Chen et al. 2010] and phase change memory (PCM) [Ho et al. 2009], has attracted

extensive interest because of their ideal properties for embedded systems: low power

consumption, high density, byte addressability, and better scalability. In particular,

PCM is arguably the most promising DRAM alternative given that it could promise

near-DRAM performance [Xie 2011; Qureshi et al. 2009b; Lee et al. 2009; Dhiman et al.

2009; Zhou et al. 2009; Lee et al. 2010; Ho et al. 2009]. There are already commercial

products available in the market [Micron 2012]. As PCM is byte addressable, software

can access PCM DIMM modules via traditional load and store instructions in the

same way as accessing DRAM [Zhou et al. 2009].

Despite its advantages, unprotected PCM has very limited write endurance com-

pared to DRAM. A PCM cell is only capable of 10

to 10

writes before wearing out

[Kang et al. 2008]. Excessive writes in PCM could also lead to high power consumption

even though read power i s in the same range as DRAM [Hay et al. 2011]. In contrast,

DRAM can sustain at least 10

writes [Lee et al. 2009]. Write reduction must be

considered for PCM to avoid fast wear-out.

Recently, architectural level techniques [Yang et al. 2007; Cho and Lee 2009] have

been introduced to avoid redundant writes in PCM: a write operation is only triggered

when the value to be written is different from the original value stored in the PCM

cell. With this type of technique, write operations will only cause bit ﬂips (the process

of changing a 0 to 1 or the other way around), avoiding writing identical values. The

lifetime of PCM is prolonged by reducing the number of writes in each cell. However,

these hardware features alone cannot satisfy the lifetime requirement of PCM-based

main memory. As Section 7 presents, with these hardware features enabled, writes to

page tables could lead to as many as ∼28,000 bit ﬂips in a single PCM cell within 1 hour.

The following calculation shows a simple, rough linear estimation for its lifetime, given

that a cell can sustain up to 10

writes:

PCM Lifetime = 10

1 hour

28,000 bit ﬂips

≈ 3,571.43 hours ≈ 5 mo nt hs.

From this calculation, the worst-case lifetime of PCM-based main memory is about

5 months. Though this is not an accurate estimation, it still reﬂects roughly the lifetime

of unprotected PCM. Most embedded systems such as those found in smartphones and

aircraft control systems obviously require a much longer lifetime. Writes in page tables

greatly reduce the lifetime of PCM-based main memory. Further reduction of unneces-

sary writes is required to increase the applicability of PCM-based main memory.

In this article, we propose write-activity-aware page table management (WAPTM),

based on the hardware features mentioned earlier for existing operating systems.

WAPTM simpliﬁes page table initialization and ﬁlls in page table entries (PTEs) with

the physical address that will cause the minimum number of bit ﬂips. We focus on

enhancing the write endurance of PCM-based main memory by redesigning write-

intensive OS components. Although it is not the only write-intensive component, page

table could be easily studied and modiﬁed. We therefore aim to reduce writes in page

tables to demonstrate the feasibility and effectiveness of prolonging PCM lifetime at

ACM Transactions on Embedded Computing Systems, Vol. 14, No. 2, Article 34, Publication date: February 2015.

Towards Write-Activity-Aware Page Table Management for Non-volatile Main Memories 34:3

the OS level. We plan to include techniques for protecting other write-intensive com-

ponents in future work. In summary, we make the following contributions:

—We present WAPTM, a set of simple yet effective modiﬁcations to existing embedded

systems, for reducing unnecessary writes in PCM-based main memory.

—In addition to the basic WAPTM algorithms, we propose and compare optimization

techniques for practical uses.

—We implement and provide a thorough evaluation for WAPTM based on Google

Android and the ARM architecture with real applications.

By deploying WAPTM in the Linux kernel for Google Android, we demonstrate the

feasibility and effectiveness of reducing writes at the OS level. This work can serve

as the ﬁrst step towards write-activity-aware OS for non-volatile main memories with

limited write endurance.

The rest of this article is organized as follows. Section 2 reviews related work at

both software and architectural levels. Section 3 then introduces and compares the

architectures of traditional DRAM-based and PCM-based embedded systems, followed

by the motivation of this work. Section 4 presents details on WAPTM. To reduce over-

head and avoid fragmentation, we propose optimization techniques for practical uses in

Section 5. Section 6 gives implementation details. Experimental results are discussed

in Section 7. Finally, we discuss future work and conclusions in Section 8.

2. RELATED WORK

There have been numerous studies to enhance the write endurance of PCM or other

non-volatile memories at both hardware and software levels.

2.1. Architecture Level

Zhou et al. [2009] proposed a set of techniques, such as redundant bit removal and row

shifting, to prolong the lifetime of PCM-based main memory. Qureshi et al. [2009b]

introduced a hybrid architecture with PCM and a s mall-sized DRAM cache. Start-Gap

[Qureshi et al. 2009a] enhances wear leveling of PCM cells by adding an additional

line. Low-power techniques [Jiang et al. 2011] are also proposed to improve PCM

endurance. Particularly, write truncation with error correction code was proposed to

improve endurance of MLC PCM [Jiang et al. 2012b].

Co-optimization with other non-volatile memories and speciﬁc applications is also

under active investigation. Sun et al. [2010] proposed a hybrid storage architecture

using PCM and ﬂash memory. It uses PCM instead of ﬂash memory to log updates

to data in ﬂash memory, thus prolonging the lifetime of ﬂash memory. PCM-FTL

[Liu et al. 2011] adopts a similar architecture to optimize both PCM and ﬂash memory.

Curling-PCM [Liu et al. 2013] utilizes application-speciﬁc features to evenly distribute

write activities across the whole PCM chip. Joo et al. [2010] proposed an energy and

endurance aware PCM cache design that reduces writes by read-before-write and data-

inverting techniques. Sun et al. [2011] utilized data locality to build frequent-value

storage. Write intensity is reduced by compressing frequently written values.

2.2. Software Level

Some software level techniques have also been proposed, such as code optimiza-

tion [Hu et al. 2013] and write-aware scheduling techniques [Hu et al. 2010]. ER

[Jiang et al. 2012a] employs data compression to prolong the lifetime of PCM.

Ferreira et al. [2010] presented write minimization, unnecessary writes reduction,

and a wear-leveling scheme to increase the lifetime of PCM-based main memory. Soft-

ware dispatch [Li et al. 2012] distributes data to different memories depending on

data access characteristics. Mogul et al. [2009] proposed an OS design for DRAM-ﬂash

ACM Transactions on Embedded Computing Systems, Vol. 14, No. 2, Article 34, Publication date: February 2015.

34:4 T. Wang et al.

Fig. 1. PCM cell structure and phase change operations.

hybrid main memory, which employs data migration techniques to improve the en-

durance of non-volatile memories. AVid [Stancu et al. 2012] also migrates data in dif-

ferent non-volatile memories, utilizing video metadata to l ower energy consumption.

ViPZonE [Bathen et al. 2012] is a system-level optimization technique for memory

allocation, focusing on reducing energy consumption in DRAM-based systems.

2.3. Comparison to Prior Work

WAPTM improves write endurance of PCM-based main memory instead of storage

systems. Different from compiler-based techniques, WAPTM utilizes architectural ad-

vances and is a pure OS-level technique, requiring no modiﬁcations to applications.

WAPTM is orthogonal to and could be used collaboratively with existing wear leveling

techniques, which usually work at a ﬁner granularity and lower level (e.g., word level).

For example, the wear leveling algorithm could provide hints such as less-used pages

and instruct WAPTM to allocate these pages ﬁrst.

3. BACKGROUND AND MOTIVATION

This section ﬁrst introduces phase change memory and PCM-based embedded systems.

A quick review of OS internals is provided for completeness. Finally, we discuss the

motivation of this work.

3.1. Phase Change Memory

Phase change memory is a type of non-volatile memory wherein a cell is made of two

electrodes and phase change materials such as Ge

(GST) [Burr et al. 2010;

Xue et al. 2011]. The phase change material can switch between amorphous (high-

resistance) and crystalline (low-resistance) states. Figure 1 shows the structure of a

PCM cell and operations to change its states. Information is stored by changing the re-

sistance of GST through applying heat stresses. Moderate-power, long-duration pulses

(“SET”) change PCM to crystalline state. High-power, shor-duration pulses (“RESET”)

change the material to amorphous state [Jiang et al. 2012b]. With repetitive heat

stresses applied, a PCM cell is only capable of sustaining a limited number of writes.

There are two types of PCM cells, namely s ingle-level cell (SLC) and multilevel cell

(MLC) [Kang et al. 2008; Bedeschi et al. 2009]. Each SLC holds only 1 bit, while each

MLC can hold 2 bits. In this work, we assume SLC is used. WAPTM could be easily

adopted by MLC once it becomes mature.

With SLC PCM-based main memory, each bit in a PTE corresponds to a PCM cell;

therefore a bit ﬂip in a PTE is equivalent to a bit ﬂip in t he corresponding PCM cell.

ACM Transactions on Embedded Computing Systems, Vol. 14, No. 2, Article 34, Publication date: February 2015.

Towards Write-Activity-Aware Page Table Management for Non-volatile Main Memories 34:5

Fig. 2. Architectures of DRAM- and PCM-based embedded systems.

In this work, we assume that hardware features [Lee et al. 2010; Yang et al. 2007; Cho

and Lee 2009] introduced in Section 1 are adopted, such that a bit ﬂip only happens

when the value to be written differs from the original value in the cell.

3.2. PCM-Based Embedded Systems

Current mainstream embedded systems use DRAM as main memory. As shown in Fig-

ure 2(a), the CPU transfers data and instructions to and from DRAM.

While the capac-

ity of DRAM keeps increasing, power consumption and density of DRAM are reaching

their limits [Xie 2011; Qureshi et al. 2009a, 2009b; Lee et al. 2009; Dhiman et al. 2009;

Zhou et al. 2009; Lee et al. 2010; Ferreira et al. 2010]. Emerging non-volatile memo-

ries have attracted extensive studies for replacing DRAM because of features such as

high-density and low-power consumption. Among various non-volatile memories, PCM

is one of the most promising to complement or replace DRAM in embedded systems.

There are already commercial PCM products available in the market [Micron 2012],

making it possible to build PCM-based embedded systems. As shown in Figure 2(b), a

PCM-based embedded system features PCM as its main memory. Software then needs

to manage and interact with PCM, instead DRAM.

3.3. Page Table Mapping

Most modern operating systems access and manage memory under the concept of

virtual memory [Silberschatz et al. 2008], which partitions the memory into ﬁxed-

sized blocks (page frames). The virtual memory is divided into pages, each of which

ﬁts exactly into one page frame. Logical addresses are translated into physical ones by

looking up per-process page tables, which are stored in multiple memory page frames.

Figure 3 presents a two-level page table design, in which a logical address is divided

into offsets in the Page Global Directory (PGD), page table, and page frame. A register

stores the base address of the PGD. Each PGD entry points to a page table which

consists of PTEs. A PTE stores the physical address of a page frame and ﬂag bits to

indicate page properties and states. For example, a 32bit ARM processor [ARM Limited

2005] uses the most signiﬁcant 20 bits to specify the address of a page frame and the

remaining bits to record properties such as whether the page is present in memory.

To access part of a page, the PGD base address is ﬁrst obtained from the register

(e.g, CR3 in Intel x86 architecture) [Intel Corporation 2013]. By adding the global

directory offset obtained from the logical address, the base address of the page table

Caching is omitted in Figure 2 for brevity.

ACM Transactions on Embedded Computing Systems, Vol. 14, No. 2, Article 34, Publication date: February 2015.

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