Ultralow-powerhigh-speedflip-flopbasedonmultimodeFinFETs资源-CSDN文库

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标题“Ultralow-power high-speed flip-flop based on multimode FinFETs”所隐含的知识点非常丰富，涉及了超低功耗、高速、触发器（Flip-Flop）、多模式鳍式场效应晶体管（FinFETs）等众多前沿的集成电路技术。下面将对这些知识点进行详细解释： 1. 鳍式场效应晶体管（FinFETs） FinFET是一种三维晶体管设计，其特点是具有一个或多个细长的硅“鳍片”，在鳍片两侧形成栅极，这种设计可以更好地控制晶体管中的电流，从而在比平面晶体管更小的尺寸下提供更好的性能和更低的漏电流。FinFET技术已经成为当今高性能半导体器件的关键技术之一，尤其是在14纳米及以下的制程技术中。本文所提到的FinFETs指的是高性能的鳍式场效应晶体管，用于制造高速且功耗极低的触发器。 2. 触发器（Flip-Flop）触发器是数字逻辑电路中最基本的存储单元，常用于构成寄存器、计数器、存储器等数字系统。在集成电路中，触发器需要具备高速和低功耗的特性，以满足日益增长的性能需求。本文介绍了新型的静态无冲突单相时钟触发器（S2CFF），这种触发器可以实现高速度和极低的功耗。 3. 超低功耗在设计集成电路时，降低功耗是非常重要的考量因素，尤其是在便携式设备和数据中心中。本文中，作者通过创新设计，成功实现了平均功耗减少高达61.8%。这对于延长电池寿命以及降低电子设备的能耗具有重要意义。 4. 高速除了低功耗，高速度同样是现代集成电路设计中的关键指标。本文所提的触发器在典型数据切换活动下的时间性能得到了显著提高，这意味着它们能够在更短的时间内完成数据处理，对于提升整个系统的运行效率至关重要。 5. 多模式（Multimode）多模式指的是FinFET晶体管可以工作在不同的模式下，以适应不同的性能需求。例如，本文中提到了短栅模式（SG-mode）和低功耗模式（LP-mode）两种不同模式的FinFETs。通过不同模式的切换，可以实现在保持速度的同时降低功耗，或是牺牲一点速度来进一步降低功耗。 6. 面向低数据切换活动的条件预充电技术为了进一步提升触发器的性能，本文提出了一种条件预充电技术，用于控制充电路径。这项技术特别针对数据切换活动低时内部节点的能量损失进行优化，减少不必要的能耗。通过采用独立门（IG-mode）FinFET作为附加控制晶体管，验证结果表明，在低数据切换活动时，功耗可以减少超过50%，同时在面积和设置时间上的惩罚是可以接受的。 7. 优化与性能提升本文还对触发器的性能进行了进一步优化，通过多模式FinFETs以及条件预充电技术的应用，有效地降低了功耗并提升了速度，同时保持了触发器的高性能标准。这对于未来集成电路设计和数字系统优化具有指导意义。通过上述的知识点，可以看出这篇文章涉及了现代集成电路设计的多个关键领域，不仅对触发器设计进行了深入研究，同时也对FinFETs的实际应用和多模式操作进行了有效的探索。这对于集成电路设计和制造，以及相关电子工程领域的发展具有重要影响。

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RESEARCH PAPER

SCIENCE CHINA

Information Sciences

April 2016, Vol. 59 042404:1–042404:11

doi: 10.1007/s11432-015-5407-6

 Science China Press and Springer-Verlag Berlin Heidelberg 2015 info.scichina.com link.springer.com

Ultralow-power high-speed ﬂip-ﬂop based on

multimode FinFETs

Kai LIAO

, Xiaoxin CUI

,NanLIAO

, Tian WANG

Dunshan YU

& Xiaole CUI

Institute of Microelectronics, Peking University, Beijing 100871,China;

Key Laboratory of Integrated Microsystems, Shenzhen Graduate School, Peking University,

Shenzhen 518055,China

Received May 11, 2015; accepted June 17, 2015; published online October 12, 2015

Abstract In this paper, we ﬁrst reconstruct a novel planar static contention-free single-phase-clocked ﬂip-

ﬂop (S

CFF) based on high-performance ﬁn-type ﬁeld-eﬀect transistors (FinFETs) to achieve high speed and

ultralow power consumption. Beneﬁting from better control of the conductive channel, the shorted-gate (SG-

mode) FinFET ﬂip-ﬂop obtains a persistent reduction of 56.7% in average power consumption as well as a

considerable improvement in timing performance at a typical 10% data switching activity, while the low-power

(LP-mode) FinFET ﬂip-ﬂop promotes the power reduction to 61.8% without appreciable degradation in speed.

However, through further analysis of the simulation results, we have revealed an unnecessary energy loss caused

by the redundant leaps of internal nodes at the static input ‘0’, which has a noticeable negative impact on total

power consumption at low data switching activity. In order to overcome this defect, a conditional precharge

technique is introduced to control the charging path, and we demonstrate that the independent-gate (IG-mode)

FinFET is the best option for the added control transistor. The veriﬁcation results indicate that our optimization

reduces the power consumption by more than 50% at low data switching activity with an acceptable area and

setup time penalty compared with that of LP-mode FinFET ﬂip-ﬂop.

Keywords multimode FinFET, ﬂip-ﬂop, ultralow-power, high-speed, high-performance

Citation Liao K, Cui X X, Liao N, et al. Ultralow-power high-speed ﬂip-ﬂop based on multimode FinFETs. Sci

China Inf Sci, 2016, 59(4): 042404, doi: 10.1007/s11432-015-5407-6

1 Introduction

Flip-ﬂops are considered one of the most essential memory types in the vast majority of digital integrated

circuits (ICs), and thus, it is extensively utilized in very large scale integration (VLSI). Under the cur-

rent circumstances, especially where high-density pipeline technology is frequently used, large numbers

of ﬂip-ﬂops have become indispensable components [1,2]. Previous researches have found that the timing

performance (including set-up time, hold time, and clock-to-output delay) of ﬂip-ﬂops has a direct eﬀect

on the clock frequency of digital circuit systems, and these irreplaceable ﬂip-ﬂops also generally consume

30%–50% of the power dissipation of the entire chip [3, 4]. Thus, high-performance ﬂip-ﬂops with the

* Corresponding author (email: cuixx@pku.edu.cn, cuixl@pkusz.edu.cn)

Liao K, et al. Sci China Inf Sci April 2016 Vol. 59 042404:2

advantages of fast speed and ultralow power consumption have been a popular research topic, and numer-

ous diﬀerent types of ﬂip-ﬂops have been invented and investigated over the past decades [5–9]. Recently,

a static contention-free single-phase-clocked (SPC) ﬂip-ﬂop (S

CFF) with low-power consumption has

been presented in [10] by Kim et al., which to our knowledge is one of the best edge-trigged ﬂip-ﬂops

implemented by traditional planar MOSFET technology in the literature.

It is well known that the total power dissipation can be divided into three major parts: dynamic power

dissipation, static power dissipation, and short-circuit power dissipation. However, with the technology

scaling down, leakage power consumption has become an increasingly important part of the total power

consumption. Since the states of ﬂip-ﬂops only switch at the rising edges of the clock signal and remain

the same at other times in the clock period, this inherent trend could be an unpleasant restriction

for advanced ﬂip-ﬂops to further reduce the power consumption. To solve this problem, several novel

multigate devices aiming at implementing ultralow leakage current have been proposed, such as ultrathin

body devices [11], fully depleted silicon on insulator (FDSOI) [12], and ﬁn-type ﬁeld-eﬀect transistors

(FinFETs) [13]. So far, FinFET seems to be the most promising option because of its superior electrical

properties and timing performance, and commercial chips based on FinFETs have already been released

by Intel, TSMC, and other global foundries.

In this article, we chose the original S

CFF based on planar MOSFET as our research object and

reconstructed it with FinFETs to achieve high speed and ultralow power consumption. At the same

time, we discovered an intrinsic defect (unnecessary energy loss) of S

CFF by analyzing the simulation

results and proposed an improvement approach by utilizing the excellent design ﬂexibility of multimode

FinFET. The veriﬁcation results show that the multimode FinFET ﬂip-ﬂop oﬀers a good solution for the

discovered defect, and the additional penalty on timing performance is acceptable.

2 FinFET devices

With the scaling down of transistor conductive channels, short-channel eﬀects (SCEs) become intoler-

able, and many multigate devices have been proposed to overcome SCEs. Due to its relatively simple

manufacturing process and good compatibility with bulk CMOS, FinFET is considered to be the most

feasible new multigate device. Through the stronger control of the conductive channel by the double

gate (front gate and back gate), the FinFET device has the advantages of higher on-state current, lower

oﬀ-state current, and faster switching speed [14, 15].

Furthermore, according to whether the front gate and back gate are tied together or not, FinFET

circuits can be divided into three diﬀerent operating modes, namely, shorted-gate (SG-mode), low-power

(LP-mode), and independent-gate (IG-mode) [16]. Diﬀerent circuit operating modes have diﬀerent char-

acteristics, which increases the design ﬂexibility. For example, the SG-mode FinFET has high on-state

current and fast switching speed to achieve high performance, while the LP-mode FinFET has low oﬀ-

state current to reduce the leakage power dissipation. Figure 1(a) and (b) illustrate the three-dimensional

diagram and cross-sectional top view of a FinFET transistor, and Figure 1(c) shows the electrical model

schematic of the three operating modes of N-FinFETs and P-FinFETs, respectively.

In our study, the simulations are based on the predictive technology model (PTM) for 32-nm Fin-

FETs [17]. PTM is a theoretical mode that ignores the actual process parameters. It covers suﬃcient

physical eﬀects, and excellent scalability of PTM across process and design conditions has been shown in

the published results. Considering there is no FinFET Spice model oﬃcially oﬀered by foundries, PTM

was selected for our study without loss of generality. The primary parameters of the devices are listed in

Table 1, which are typical for manufactured 32-nm FinFETs. The parameter L

gate

denotes the length of

the gate, while H

ﬁn

and W

ﬁn

denote the height and width of the silicon ﬁn, respectively. For a common

SG-mode FinFET, the equivalent gate width W

gate

can be calculated by

gate

=2× H

ﬁn

+ W

ﬁn

. (1)

Note that, W

ﬁn

is usually much smaller than H

ﬁn

, and for LP- and IG-mode FinFETs, W

ﬁn

is eliminated

because the top silicon of the gate is polished to separate the double gates. In addition, the thickness of

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