18308045_谷正阳_第五次实验1

input [15:0] data;

output [3:0] sm_wei;

output [6:0] sm_duan;

//----------------------------------------------------------

reg clk_400Hz; always

@(posedge clk)

reg [3:0]wei_ctrl=4'b1110; always

@(posedge clk_400Hz)

reg [3:0]duan_ctrl;

always @(wei_ctrl)

case(wei_ctrl)

4'b1110:duan_ctrl=data[3:0];

//----------------------------------------------------------

reg [7:0]duan;

always @(duan_ctrl)

case(duan_ctrl)

4'h0:duan=7'b100_0000;//0 4'h1:duan=7'b111_1001;//1

4'h2:duan=7'b010_0100;//2 4'h3:duan=7'b011_0000;//3

4'h4:duan=7'b001_1001;//4 4'h5:duan=7'b001_0010;//5

default : duan = 7'b100_0000;//0

endcase

//----------------------------------------------------------

assign sm_wei = wei_ctrl;

assign sm_duan = duan;

endmodule

disply_0.veo.