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计算结构CPU报告_04016613裘文成_04016640_薛家龙1

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计算结构CPU报告_04016613裘文成_04016640_薛家龙1

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Computer Organization and Architecture

School of Information Science and Engineering

Southeast University

April 2019

Microprogrammed CPU Design

Group members:

04016613 Wencheng Qiu

04016640 Jialong Xue

1.Purpose

The purpose of this project is to design and verify a simple CPU (Central Processing

Unit). This CPU has basic instruction set, and we will utilize its instruction set to

generate a very simple program to verify its performance. For simplicity, we will only

consider the relationship among the CPU, registers, memory and instruction set. That

is to say we only need consider the following items: Read/Write Registers, Read/Write

Memory and Execute the instructions.

At least four parts constitute a simple CPU: the control unit, the internal registers, the

ALU and instruction set, which are the main aspects of our project design and will be

studied.

2.Tasks

2.1 Main tasks

Single-address instruction format is used in our simple CPU design. The instruction

word contains two sections: the operation code (opcode), which defines the function of

instructions (addition, subtraction, logic operations, etc.); the address part, in most

instructions, the address part contains the memory location of the datum to be operated,

we called it direct addressing. In some instructions, the address part is the operand,

which is called immediate addressing.

For simplicity, the size of memory is 256×16 in the computer. The instruction word has

16 bits. The opcode part has 8 bits and address part has 8 bits. The instruction word

format can be expressed in Figure 1

OPCODE

[15…8]

ADDRESS

[7…0]

Figure 1 The instruction format

The opcode of the relevant instructions are listed in Table 1.

Table 1 List of instructions and relevant opcodes

Instruction

OPCODE

Comments

STORE X

00000001

ACC->[X]

LOAD X

00000010

[X]->ACC

ADD X

00000011

ACC+[X]->ACC

SUB X

00000100

ACC-[X]->ACC

JMPGEZ X

00000101

If ACC≥0 then X->PC else PC+1->PC

JMP X

00000110

X->PC

HALT

00000111

Halt a program

MPY X

00001000

ACC×[X]->ACC

DIV X

00001001

ACC÷[X]->ACC

AND X

00001010

ACC and [X]->ACC

OR X

00001011

ACC or [X]->ACC

NOT X

00001100

NOT [X]->ACC

SHIFTR

00001101

SHIFT ACC to Right 1bit,Logic Shift

SHIFTL

00001110

SHIFT ACC to Left 1bit,Logic Shift

……

Figure 2 Control Unit Micro-architecture

Figure 2 shows the key elements of such an implementation. The set of

microinstructions is stored in the control memory. The control address register contains

the address of the next microinstructions to be read. When a microinstruction is read

from the control memory, it is transferred to a control buffer register, the register

connects to the control lines emanating from the control unit. Thus, reading a

microinstruction from the control memory is the same as executing that

microinstruction. The third element shown in the figure is a sequencing unit that loads

the control address register and issues a read command.

Figure 3 CPU data path and control signals

Figure 3 indicates a simple CPU architecture and its use of a variety of internal data

paths and control signals. Our CPU design should be based on this architecture.

ACC

ALU

Control

signals

Control

Unit

Flags

Control

Signals

3.Top module form

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