9.2.3. Interfaces............................................................................................... 88
9.2.4. Operation............................................................................................... 88
9.3. Parameter...........................................................................................................89
9.4. Configuration Registers.........................................................................................89
9.5. Interface Signals..................................................................................................89
9.6. Ethernet MDIO Core Revision History......................................................................90
10. Intel FPGA 16550 Compatible UART Core....................................................................91
10.1. Core Overview...................................................................................................91
10.2. Feature Description............................................................................................ 91
10.2.1. Unsupported Features.............................................................................92
10.2.2. Interface...............................................................................................92
10.2.3. General Architecture...............................................................................94
10.2.4. 16550 UART General Programming Flow Chart........................................... 94
10.2.5. Configuration Parameters........................................................................ 96
10.2.6. DMA Support......................................................................................... 96
10.2.7. FPGA Resource Usage............................................................................. 97
10.2.8. Timing and Fmax................................................................................... 97
10.2.9. Avalon-MM Slave....................................................................................98
10.2.10. Over-run/Under-run Conditions.............................................................. 99
10.2.11. Hardware Auto Flow-Control.................................................................100
10.2.12. Clock and Baud Rate Selection..............................................................101
10.3. Software Programming Model.............................................................................101
10.3.1. Overview.............................................................................................101
10.3.2. Supported Features.............................................................................. 101
10.3.3. Unsupported Features........................................................................... 102
10.3.4. Configuration....................................................................................... 102
10.3.5. 16550 UART API...................................................................................102
10.3.6. Driver Examples...................................................................................106
10.4. Address Map and Register Descriptions ...............................................................110
10.4.1. rbr_thr_dll...........................................................................................111
10.4.2. ier_dlh................................................................................................ 112
10.4.3. iir.......................................................................................................114
10.4.4. fcr......................................................................................................115
10.4.5. lcr...................................................................................................... 117
10.4.6. mcr.................................................................................................... 119
10.4.7. lsr...................................................................................................... 120
10.4.8. msr.................................................................................................... 122
10.4.9. scr..................................................................................................... 124
10.4.10. afr.................................................................................................... 125
10.4.11. tx_low...............................................................................................126
10.5. Intel FPGA 16550 Compatible UART Core Revision History......................................126
11. UART Core.................................................................................................................128
11.1. Core Overview................................................................................................. 128
11.2. Functional Description.......................................................................................128
11.2.1. Avalon-MM Slave Interface and Registers.................................................128
11.2.2. RS-232 Interface..................................................................................129
11.2.3. Transmitter Logic..................................................................................129
11.2.4. Receiver Logic......................................................................................129
11.2.5. Baud Rate Generation........................................................................... 130
Contents
Embedded Peripherals IP User Guide
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