4
Figure 1：设计方案层次结构 ..........................................................................................................................8
Figure 2：自制 jtag pmod 转接板 .................................................................................................................9
Figure 3：项目整体硬件连接 ..........................................................................................................................9
Figure 4：E203 流水线结构 ........................................................................................................................ 10
Figure 5：E203Plus SoC 组成 ...................................................................................................................... 12
Table 1：E203Plus SoC 物理内存分配 .................................................................................................... 12
Table 2：E203Plus Soc 资源占用 .............................................................................................................. 13
Figure 6：程序流程图 .................................................................................................................................... 15
Table 3：ICB Bridge 模块 IO 接口定义.................................................................................................... 16
Figure 7：DDR3 内存扩容连接关系 ......................................................................................................... 18
Figure 8：ICB Bridge 实现框图 .................................................................................................................. 19
Figure 9：ICB Bridge 状态转移图 ............................................................................................................. 20
Figure 10：按字节存入数据行为仿真 ...................................................................................................... 20
Figure 11：按字节读出数据行为仿真 ...................................................................................................... 21
Figure 12：DDR 内存扩展 FPGA 原型测试 ............................................................................................ 21
Figure 13：EMAC 外设发送缓冲区地址映射 ........................................................................................ 22
Figure 14：EMAC 外设接收缓冲区地址映射 ......................................................................................... 22
Table 4：EMAC 外设寄存器 ........................................................................................................................ 22
Table 5：EMAC 模块 IO 接口定义 ............................................................................................................ 22
Figure 15：EMAC 模块连接关系 ................................................................................................................ 24
Figure 16：以太网发送行为仿真................................................................................................................ 24
Figure 17：以太网接收行为仿真................................................................................................................ 25
Figure 18：EMAC 外设 FPGA 原型测试 ................................................................................................... 26
Figure 19：KNN Accelerator 地址映射 ................................................................................................... 27
Figure 20：KNN Accelerator 连接关系 ................................................................................................... 28
Figure 21：KNN Accelerator 实现框图 ................................................................................................... 29
Figure 22：KNN Accelerator 状态转移图 ............................................................................................... 29
Figure 23： KNN XOR 与 COUNT 状态行为仿真................................................................................. 30
Figure 24：KNN SUM 与 RSP 状态行为仿真 .......................................................................................... 30
Table 6：VGA Controller 模块 IO 接口定义 .......................................................................................... 31
Figure 25：VGA Controller 连接关系 ...................................................................................................... 31
Figure 26：VGA 模块 FPGA 原型测试 ...................................................................................................... 33
Figure 27：GPIO 不按按键 .......................................................................................................................... 37
Figure 28：GPIO button0 对应红色 led ................................................................................................... 38
Figure 29：GPIO button1 对应绿色 led .................................................................................................. 38
Figure 30：GPIO button2 对应蓝色 led’ ................................................................................................. 39
Figure 31：RISC-V 字样显示测试 .............................................................................................................. 39
Figure 32：以太网 UDP 报文回传测试 .................................................................................................... 40
Figure 33：tftp 文件传输测试（下载） ................................................................................................... 41
Figure 34：tftp 文件传输测试（上传） ................................................................................................... 41
Figure 35：身份证号识别任务硬件连接 .................................................................................................. 42
Figure 36：身份证号识别任务 tftp 服务器 log .................................................................................... 43
Figure 37：身份证号识别任务 txt 结果................................................................................................... 43
Figure 38：身份证号识别任务显示器显示结果 .................................................................................... 44
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