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We describe a hardware-oriented design of a complex division algorithm proposed in .6 This algorithm is similar to a radix-r digit-recurrence division algorithm with real operands and prescaling. Prescaling of complex operands allows efficient selection of complex quotient digits in higher radix. The use of the digit-recurrence method allows hardware implementation similar to that of conventional dividers. Moreover, this method makes correct rounding of complex quotient possible. On the other hand, the proposed scheme requires the use of prescaling tables which are more demanding than tables in similar dividers with real operands. In this paper we present main design ideas, implementation details, and give a rough estimate of the expected latency. We also make a comparison with the estimated latency of the Smith’s algorithm used in software routines for complex division. 基于给定文件的内容，以下是对复杂数字除法器设计的知识点总结：复杂数字除法器的设计主要分为硬件和软件两种实现方式。在硬件实现领域，复杂数字除法器通常不如复杂数字乘法器常见。传统的软件实现在处理复数除法时，可能会在中间计算过程中发生溢出，即使最终结果在浮点格式中是可表示的。为了解决这一问题，人们提出了多种算法，比如Smith算法，该算法采用更鲁棒的公式来避免在中间计算过程中出现溢出，并且在最终结果中保证了正确的实数部分的四舍五入。然而，本文提出了一种新的硬件设计，针对复数除法算法，它类似于基于基数-r的数字递归除法算法，该算法适用于实数运算，并加入了预缩放技术。复数的预缩放使得在较高基数的情况下可以更高效地选择复数商的数字。采用数字递归方法，硬件实现可以类似于传统的除法器。此外，该方法还允许进行复数商的正确四舍五入。提出的设计方案需要使用预缩放表，这些表比仅处理实数运算的除法器中使用的表更为复杂。本文详细介绍了主要的设计思想、实现细节，并提供了一个大致的预期延迟估算。同时，还与软件程序中使用的Smith算法的估计延迟进行了比较。在信号处理和通信系统中，复数除法的硬件实现对于提高系统的性能至关重要。与软件实现相比，硬件实现可以显著提高计算速度并降低延迟，这对于实时系统尤其重要。数字递归算法基于迭代的方法，通常用于实现除法器。这种方法的优势在于，尽管每次迭代只产生一个商位，但是设计可以并行化，从而提高运算速度。该方法通常需要查找表来帮助选择商的每一位数字，这在本文中提到的预缩放表中表现得尤为明显。预缩放是处理复数除法时的关键技术之一。它涉及到调整除数，以简化随后的计算步骤。预缩放可以减少所需的迭代次数，并且可以减少运算过程中的错误传播。这种技术允许在更高的基数下有效选择复数商数字，从而提高了运算效率。在复数除法器的硬件设计中，流水线技术的使用是为了实现更高的吞吐量和更好的时钟频率。流水线技术通过将复杂的运算分解为几个较简单的步骤，并在连续的时钟周期内逐步完成这些步骤来实现。这种方法有助于优化资源使用，减少延迟，并且可以提高设备的总体性能。关键词中提及的"radix-r"表示基数为r，这指的是一种特定的数字递归除法算法的基础，其中r代表基数的大小。而在"hardware implementation"中，硬件实现指的是使用硬件电路来实现算法的过程，这种方法通常比软件实现更快，更有效率，尤其在对速度和延迟要求高的场合。本文提出的复杂数字除法器的设计是一种结合了预缩放技术、数字递归方法和硬件实现优势的先进解决方案。这种设计不仅能够提高运算效率和减少延迟，还能够确保运算结果的精确性和可靠性。对于涉及复杂数学运算的应用场景，这种硬件设计方案具有明显的优势和广阔的应用前景。

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Design of a complex divider

Miloˇs D. Ercegovac

and Jean-Michel Muller

Computer Science Department, University of California, Los Angeles, California, U.S.A.;

CNRS-Laboratoire CNRS-ENSL-INRIA-UCBL LIP, Ecole Normale Superieure de Lyon,

Lyon, France

ABSTRACT

We describe a hardware-oriented design of a complex division algorithm proposed in .

This algorithm is

similar to a radix-r digit-recurrence division algorithm with real operands and prescaling. Prescaling of complex

operands allows eﬃcient selection of complex quotient digits in higher radix. The use of the digit-recurrence

method allows hardware implementation similar to that of conve ntional dividers. Moreover, this method makes

correct rounding of complex quotient possible. On the other hand, the prop osed scheme requires the use of

prescaling tables which are more demanding than tables in similar dividers with real operands. In this paper we

present main design ideas, implementation details, and give a rough estimate of the expected latency. We also

make a comparison with the estimated latency of the Smith’s algorithm used in software routines for complex

division.

Keywords: Complex division, digit-recurrence algorithms, prescaling, radix r, hardware implementation

1. INTRODUCTION

As mentioned in,

complex division is used in diverse applications such as earthfault distance protection,

acoustic pulse reﬂectometry,

astronomy,

non-linear RF measurement,

as well as in many digital s ignal

processing applications such as the complex SVD . While hardware implementations of complex multipliers are

common, complex division has been largely provided in software.

A software routine using the conventional formula

a + ib

c + id

ac + bd + i(bc − ad)

+ d

. (1)

may lead to overﬂows during the intermediate computations although the ﬁnal result is representable in the

ﬂoating-p oint format. This drawback has been discussed in

1, 10

and by Smith

who proposed a more robust

algorithm:

a + ib

c + id











a + b(d/c)

c + d(d/c)

+ i

b − a(d/c)

c + d(d/c)

( if |c| ≥ |d|)

b + a(c/d)

d + c(c/d)

+ i

a − b(c/d)

d + c(c/d)

( if |c| ≤ |d|)

(2)

Stewart

prop os es further improvements to the Smith’s algorithm resulting in even more complicated algo-

rithm. In spite of their robustness, these algorithms c annot guarantee correct rounding of the real and imaginary

parts of the quotient. A direct hardware implementation of the Smith’s or Stewart’s algorithms is not attractive

since it would require costly hardware implementation without signiﬁcant performance gain over software-based

solutions.

Hardware algorithms and implementations for complex division have not been studied frequently. A hardware

implementation of complex division has been developed in

using a radix-2 on-line algorithm and implemented

Further author information: (Send correspondence to M.D.E.)

M.D.E.: E-mail: milos@cs.ucla.edu, Telephone: 1 310 825 5414

J.-M.M.: E-mail: Jean-Michel.Muller@ens-lyon.fr

(1) on a reconﬁgurable hardware. This approach, however, is not suitable for higher radices because it uses

quotient-digit selection function with selection constants.

The key idea of the approach proposed in

is to apply a high-radix (real) digit-recurrence division algorithm

with prescaling of operands

4, 5

to complex division. That is, the proposed division algorithm uses a standard

residual recurrence with complex variables

w[j + 1] = rw[j] − q

j+1

y (3)

where w[0] = x is the complex dividend, y is the complex divisor, and the complex quotient digits q

’s are chosen

in a radix-r redundant digit-set, so that the complex residuals w[j] remain bounded.

Several approaches to quotient-digit selection in high radix division algorithms have been discussed in the

literature.

Among them, the prescaling technique is most suitable for higher radix: it consists of multiplying

the dividend x and the divisor y by a constant K such that Ky is close to 1. Consequently, one can choose q

j+1

by rounding rw[j] (or its low-precision estimate) to the nearest integer.

In the rest of the paper we ﬁrst review the algorithm for complex division. Then we discuss a design and

implementation details followed by a rough estimate of the expected cycle time and overall latency. We compare

these estimates with delay characteristics of compatible dividers operating on real operands.

Throughout the paper, i is

√

−1, and if z is a complex number, then zR = Re(z) and zI = Im(z) denote the

real and imaginary parts of z. The norm ||z||

∞

denotes max{|zR|, |zI|}, whereas |z| denotes the usual com plex

absolute value

(zR)

+ (zI)

2. COMPLEX DIVISION ALGORITHM - AN OVERVIEW

2.1. General scheme

The algorithm for complex division developed in

computes

q = qR + iqI = z/d =

zR + izI

dR + idI

(4)

by performing the following steps:

Prescaling. Obtain a complex scaling factor K = K1 + iK2 as a short approximation of 1/d such that

||Kd − 1||

∞

< 2

−p

(5)

where the integer p depends on the radix r. Then, compute scaled c omplex dividend and divisor



w[0] = zK

y = dK

(6)

Prescaling of the divisor and dividend allows simpliﬁed and separate selection of the real and imaginary

parts of the complex quotient digits.

Iterations. Perform radix-r = 2

iterations to produce n + 1 quotient digits

w[j + 1] = rw[j] − q

j+1

y (7)

where r is the radix of the division, q

j+1

= qR

j+1

+ iqI

j+1

, and qR

j+1

and qI

j+1

belong to the redundant

digit-set DS = {−a, . . . , a}.

Any choice of the q

’s for which the ||w[j]||

∞

’s remain bounded l suﬃces to produce the quotient digits

satisfying

0.qR

···qR

+ i0.qI

···qI

→ z/d

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