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标题与描述中的关键词“pxa270pdf”指向了Intel PXA270处理器的数据手册，这份资料详细介绍了Intel PXA270处理器的技术规格、电气特性、机械设计及热管理规范，对于理解该处理器的功能与应用具有重要的参考价值。 ### 重要知识点 #### 高性能处理器架构 - **Intel XScale微架构**：Intel PXA270处理器基于Intel XScale微架构，这一架构提供了高性能计算能力，同时保持低功耗特性。 - **7阶段流水线**：提高了指令处理效率，加速了数据吞吐量。 - **缓存结构**：包括32KB指令缓存、32KB数据缓存以及2KB“迷你”数据缓存，这些缓存提高了数据访问速度，减少了延迟。 - **数据缓冲技术**：通过扩展数据缓冲来提升数据处理速度和系统响应时间。 #### 内部SRAM - **256KB内部SRAM**：用于高速代码或数据存储，在低功耗模式下仍能保持数据不丢失。 #### 基带处理器接口 - **Mobile Scalable Link**：这是一种高速基带处理器接口，用于实现高速数据传输，支持多种通信标准。 #### 丰富的串行外设集 - 包括AC’97音频端口、I2S音频端口、USB客户端控制器、USB主机控制器、USB On-The-Go控制器、三个高速UART（其中两个带有硬件流控制）、红外通信端口等，提供了多样化的外设连接选项。 #### 硬件调试与监控功能 - **IEEE JTAG接口**：支持边界扫描，便于硬件调试。 - **内置跟踪缓冲器**：用于硬件性能监控。 #### 实时与操作系统定时器 - **实时时钟**：提供精确的时间基准。 - **操作系统定时器**：支持各种操作系统的时间管理需求。 #### LCD控制器与USIM接口 - **LCD控制器**：用于驱动LCD显示屏，支持复杂图形界面。 - **USIM接口**：用于连接通用用户身份模块，增强安全性。 #### 能耗管理 - **无线Intel SpeedStep技术**：动态调整电压和频率，优化能耗。 - **典型内部功耗小于500mW**：表明其在低功耗设计上的出色表现。 - **可降至0.85V的供电电压**：进一步降低了功耗。 - **四种低功耗模式**：提供不同场景下的节能策略。 - **动态电压与频率管理**：根据工作负载自动调整，达到节能效果。 #### 内存控制器 - 支持四银行SDRAM，最高可达104MHz的运行速度，适应不同的电源电压（2.5V、3.0V、3.3V）。 - 六个静态芯片选择，支持PCMCIA和Compact Flash，增强了内存扩展性和兼容性。 #### 多功能时钟管理 - CPU时钟频率范围为104MHz至624MHz，提供灵活的内存时钟比例，支持频率变化和功能时钟门控。 #### 系统连接性 - 包括SD卡/MMC控制器、Memory Stick卡控制器、三个SSP控制器、两个I2C控制器、四个PWM、按键接口等，极大地丰富了系统的连接选项，提升了设备的灵活性和扩展性。 Intel PXA270处理器凭借其高性能、低功耗、丰富的外设接口和灵活的时钟管理，成为移动设备、嵌入式系统和其他高性能应用的理想选择。

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Intel® PXA270 Processor

Electrical, Mechanical, and Thermal Specification

Data Sheet

n High-performance processor:

—Intel XScale® microarchitecture with

Intel® Wireless MMX™ Technology

—7 Stage pipeline

—32 KB instruction cache

—32 KB data cache

—2 KB “mini” data cache

—Extensive data buffering

n 256 Kbytes of internal SRAM for high

speed code or data storage preserved

during low-power states

n High-speed baseband processor interface

(Mobile Scalable Link)

n Rich serial peripheral set:

—AC’97 audio port

—I

S audio port

—USB Client controller

—USB Host controller

—USB On-The-Go controller

—Three high-speed UARTs (two with

hardware flow control)

—FIR and SIR infrared communications

port

n Hardware debug features — IEEE JTAG

interface with boundary scan

n Hardware performance-monitoring

features with on-chip trace buffer

n Real-time clock

n Operating-system timers

n LCD Controller

n Universal Subscriber Identity Module

interface

n Low power:

—Wireless Intel Speedstep® Technology

—Less than 500 mW typical internal

dissipation

—Supply voltage may be reduced to

0.85 V

—Four low-power modes

—Dynamic voltage and frequency

management

n High-performance memory controller:

—Four banks of SDRAM: up to 104 MHz

@ 2.5V, 3.0V, and 3.3V I/O interface

—Six static chip selects

—Support for PCMCIA and Compact

Flash

—Companion chip interface

n Flexible clocking:

—CPU clock from 104 to 624 MHz

—Flexible memory clock ratios

—Frequency changes

—Functional clock gating

n Additional peripherals for system

connectivity:

—SD Card / MMC Controller (with SPI

mode support)

—Memory Stick card controller

—Three SSP controllers

—Two I

C controllers

—Four pulse-width modulators (PWMs)

—Keypad interface with both direct and

matrix keys support

—Most peripheral pins double as GPIOs

Order Number 280002-002

ii Electrical, Mechanical, and Thermal Specification

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL

PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY

ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN

INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS

ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES

RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER

INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined. Intel reserves these for

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The PXA270

processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current

characterized errata are available on request.

This document and the software described in it are furnished under license and may only be used or copied in accordance with the terms of the

license. The information in this document is furnished for informational use only, is subject to change without notice, and should not be construed as a

commitment by Intel Corporation. Intel Corporation assumes no responsibility or liability for any errors or inaccuracies that may appear in this

document or any software that may be provided in association with this document. Except as permitted by such license, no part of this document may

be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling

1-800-548-4725 or by visiting Intel's website at http://www.intel.com.

AlertVIEW, AnyPoint, AppChoice, BoardWatch, BunnyPeople, CablePort, Celeron, Chips, CT Connect, CT Media, Dialogic, DM3, EtherExpress,

ETOX, FlashFile, i386, i486, i960, iCOMP, InstantIP, Intel, Intel logo, Intel386, Intel486, Intel740, IntelDX2, IntelDX4, IntelSX2, Intel Create & Share,

Intel GigaBlade, Intel InBusiness, Intel Inside, Intel Inside logo, Intel NetBurst, Intel NetMerge, Intel NetStructure, Intel Play, Intel Play logo, Intel

SingleDriver, Intel SpeedStep, Intel StrataFlash, Intel TeamStation, Intel Xeon, Intel XScale, IPLink, Itanium, LANDesk, LanRover, MCS, MMX, MMX

logo, Optimizer logo, OverDrive, Paragon, PC Dads, PC Parents, PDCharm, Pentium, Pentium II Xeon, Pentium III Xeon, Performance at Your

Command, RemoteExpress, Shiva, SmartDie, Solutions960, Sound Mark, StorageExpress, The Computer Inside., The Journey Inside,

TokenExpress, Trillium, VoiceBrick, Vtune, and Xircom are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United

States and other countries.

*Other names and brands may be claimed as the property of others.

Intel® PXA270 Processor

Contents

Electrical, Mechanical, and Thermal Specification iii

Contents

1 Introduction .........................................................................................................1-1

1.1 About This Document.................................................................................1-1

1.1.1 Number Representation ................................................................1-1

1.1.2 Typographical Conventions ...........................................................1-1

1.1.3 Applicable Documents...................................................................1-2

2 Functional Overview ...........................................................................................2-1

3 Package Information...........................................................................................3-1

3.1 Package Information ..................................................................................3-1

3.2 Processor Materials....................................................................................3-6

3.3 Junction To Case Temperature Thermal Resistance.................................3-7

3.4 Processor Markings....................................................................................3-7

3.5 Tray Drawing ..............................................................................................3-8

4 Pin Listing and Signal Definitions .....................................................................4-1

4.1 Ball Map View.............................................................................................4-2

4.1.1 13x13 mm VF-BGA Ball map ........................................................4-2

4.1.2 23x23 mm PBGA Ball map............................................................4-6

4.2 Pin Usage...................................................................................................4-9

4.3 Signal Types.............................................................................................4-27

4.4 Memory Controller Reset and Initialization...............................................4-28

4.5 Power-Supply Pins ...................................................................................4-29

5 Electrical Specifications.....................................................................................5-1

5.1 Absolute Maximum Ratings........................................................................5-1

5.2 Operating Conditions..................................................................................5-1

5.2.1 Internal Power Domains ................................................................5-6

5.3 Power-Consumption Specifications............................................................5-6

5.4 DC Specification.........................................................................................5-8

5.5 Oscillator Electrical Specifications..............................................................5-9

5.5.1 32.768-kHz Oscillator Specifications .............................................5-9

5.5.2 13.000-MHz Oscillator Specifications..........................................5-11

5.6 CLK_PIO and CLK_TOUT Specifications ................................................5-12

5.7 48 MHz Output Specifications ..................................................................5-13

6 AC Timing Specifications ...................................................................................6-1

6.1 AC Test Load Specifications ......................................................................6-1

6.2 Reset and Power Manager Timing Specifications......................................6-2

6.2.1 Power-On Timing Specifications ...................................................6-2

6.2.2 Hardware Reset Timing.................................................................6-4

6.2.3 Watchdog Reset Timing ................................................................6-5

6.2.4 GPIO Reset Timing .......................................................................6-5

6.2.5 Sleep Mode Timing .......................................................................6-6

6.2.6 Deep-Sleep Mode Timing..............................................................6-7

Intel® PXA270 Processor

Contents

iv Electrical, Mechanical, and Thermal Specification

6.2.7 Standby-Mode Timing .................................................................6-10

6.2.8 Idle-Mode Timing.........................................................................6-10

6.2.9 Frequency-Change Timing..........................................................6-10

6.2.10 Voltage-Change Timing...............................................................6-11

6.3 GPIO Timing Specifications .....................................................................6-11

6.4 Memory and Expansion-Card Timing Specifications................................6-12

6.4.1 Internal SRAM Read/Write Timing Specifications .......................6-12

6.4.2 SDRAM Parameters and Timing Diagrams.................................6-12

6.4.3 ROM Parameters and Timing Diagrams .....................................6-18

6.4.4 Flash Memory Parameters and Timing Diagrams.......................6-23

6.4.5 SRAM Parameters and Timing Diagrams ...................................6-33

6.4.6 Variable-Latency I/O Parameters and Timing Diagrams.............6-36

6.4.7 Expansion-Card Interface Parameters and Timing Diagrams.....6-40

6.5 LCD Timing Specifications .......................................................................6-43

6.6 SSP Timing Specifications .......................................................................6-44

6.7 JTAG Boundary Scan Timing Specifications............................................6-45

Glossary.............................................................................................................Glossary-1

Figures

2-1 Intel® PXA270 Processor Block Diagram, Typical System................................2-2

3-1 13x13mm VF-BGA Intel® PXA270 Processor Package, top view .....................3-1

3-2 13x13mm VF-BGA Intel® PXA270 Processor Package, bottom view ...............3-2

3-3 13x13mm VF-BGA Intel® PXA270 Processor Package, side view ...................3-3

3-4 VF-BGA Product Information Decoder...............................................................3-3

3-5 23x23 mm PBGA Intel® PXA270 Processor Package (Top View) ....................3-4

3-6 23x23 mm PBGA Intel® PXA270 Processor Package (Bottom View) ...............3-4

3-7 23x23 mm PBGA Intel® PXA270 Processor Package (Side View) ...................3-5

3-8 PBGA Product Information Decoder ..................................................................3-5

3-9 13x13mm VF-BGA Intel® PXA270 Processor Package, bottom view ...............3-6

3-10Intel® PXA270 Processor Production Markings, (Laser Mark on Top Side)......3-7

4-1 13x13 mm VF-BGA Ball Map, Top View (upper left quarter) .............................4-2

4-2 13x13 mm VF-BGA Ball Map, Top View (upper right quarter) ...........................4-3

4-3 13x13 mm VF-BGA Ball Map, Top View (bottom left quarter) ...........................4-4

4-4 13x13 mm VF-BGA Ball Map, Top View (bottom right quarter) ........................4-5

4-5 23x23 mm PBGA Ball Map, Top View (Upper Left Quarter) ..............................4-6

4-6 23x23 mm PBGA Ball Map, Top View (Upper Right Quarter)............................4-7

4-7 23x23 mm PBGA Ball Map, Top View (Lower Left Quarter) ..............................4-8

4-8 23x23 mm PBGA Ball Map, Top View (Lower Right Quarter)............................4-9

6-1 AC Test Load .....................................................................................................6-2

6-2 Power On Reset Timing .....................................................................................6-3

6-3 Hardware Reset Timing .....................................................................................6-4

6-4 GPIO Reset Timing ............................................................................................6-5

6-5 Sleep Mode Timing ............................................................................................6-7

6-6 Deep-Sleep-Mode Timing ..................................................................................6-8

6-7 SDRAM Timing ................................................................................................6-15

6-8 SDRAM 4-Beat Read/4-Beat Write, Different Banks Timing............................6-16

6-9 SDRAM 4-Beat Write/4-Beat Write, Same Bank-Same Row Timing ...............6-17

6-10SDRAM Fly-by DMA Timing.............................................................................6-18

Intel® PXA270 Processor

Contents

Electrical, Mechanical, and Thermal Specification v

6-1132-Bit Non-burst ROM, SRAM, or Flash Read Timing .....................................6-20

6-1232-Bit Burst-of-Eight ROM or Flash Read Timing ............................................6-21

6-13Eight-Beat Burst Read from 16-Bit Burst-of-Four ROM or Flash Timing..........6-22

6-1416-bit ROM/Flash/SRAM Read for 4/2/1 Bytes Timing ....................................6-23

6-15Synchronous Flash Burst-of-Eight Read Timing ..............................................6-26

6-16Synchronous Flash Stacked Burst-of-Eight Read Timing ................................6-27

6-17First-Access Latency Configuration Timing......................................................6-28

6-18Synchronous Flash Burst Read Example.........................................................6-30

6-1932-Bit Flash Write Timing .................................................................................6-31

6-2032-Bit Stacked Flash Write Timing ...................................................................6-32

6-2116-Bit Flash Write Timing .................................................................................6-33

6-2232-Bit SRAM Write Timing ...............................................................................6-35

6-2316-bit SRAM Write for 4/2/1 Byte(s) Timing .....................................................6-36

6-2432-Bit VLIO Read Timing .................................................................................6-38

6-2532-Bit VLIO Write Timing..................................................................................6-39

6-26Expansion-Card Memory or I/O 16-Bit Access Timing.....................................6-41

6-27Expansion-Card Memory or I/O 16-Bit Access to 8-Bit Device Timing ............6-42

6-28LCD Timing Definitions.....................................................................................6-43

6-29SSP Master Mode Timing Definitions...............................................................6-44

6-30SSP Slave Mode Transmitting Data to an External Peripheral ........................6-44

6-31SSP Slave Mode Receiving Data from External Peripheral .............................6-45

6-32JTAG Boundary-Scan Timing...........................................................................6-46

Tables

1-1 Supplemental Documentation ............................................................................1-2

3-1 Processor Material Properties ............................................................................3-7

4-1 Pin Usage Summary ........................................................................................4-10

4-2 Pin Usage and Mapping Notes.........................................................................4-27

4-3 Signal Types.....................................................................................................4-28

4-4 Memory Controller Pin Reset Values ...............................................................4-28

4-5 Discrete (13x13 VF-BGA) Power Supply Pin Summary...................................4-29

5-1 Absolute Maximum Ratings................................................................................5-1

5-2 Voltage, Temperature, and Frequency Electrical Specifications........................5-2

5-3 Memory Voltage and Frequency Electrical Specifications .................................5-4

5-4 Core Voltage and Frequency Electrical Specifications.......................................5-4

5-5 Internally Generated Power Domain Descriptions .............................................5-6

5-6 Core Voltage Specifications For Lower Power Modes .......................................5-6

5-7 Power-Consumption Specifications....................................................................5-7

5-8 Standard Input, Output, and I/O Pin DC Operating Conditions ..........................5-8

5-9 Typical 32.768-kHz Crystal Requirements .........................................................5-9

5-10 Typical External 32.768-kHz Oscillator Requirements ....................................5-11

5-11Typical 13.000-MHz Crystal Requirements......................................................5-11

5-12Typical External 13.000-MHz Oscillator Requirements....................................5-12

5-13CLK_PIO Specifications ...................................................................................5-12

5-14CLK_TOUT Specifications ...............................................................................5-12

5-1548 MHz Output Specifications ..........................................................................5-13

6-1 Standard Input, Output, and I/O-Pin AC Operating Conditions ..........................6-1

6-2 Power-On Timing Specifications (OSCC[CRI] = 0) ............................................6-3

6-3 Hardware Reset Timing Specifications (OSCC[CRI] = 0) ..................................6-4

6-4 Hardware Reset Timing Specifications (OSCC[CRI] = 1) .................................6-5

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