UM10237
LPC24XX User manual
Rev. 04 — 26 August 2009 User manual
Document information
Info Content
Keywords LPC2400, LPC2458, LPC2420, LPC2460, LPC2468, LPC2470, LPC2478,
ARM, ARM7, 32-bit, Single-chip, External memory interface, USB 2.0,
Device, Host, OTG, Ethernet, CAN, I2S, I2C, SPI, UART, PWM, IRC,
Microcontroller
Abstract LPC24XX User manual release
UM10237_4 © NXP B.V. 2009. All rights reserved.
User manual Rev. 04 — 26 August 2009 2 of 792
Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors
UM10237
LPC24XX User manual
Revision history
Rev Date Description
04 20090826 LPC24XX user manual release.
Modifications:
• Memory size for LPC2458 external SRAM memory corrected in Table 2–14.
• Deep power-down mode functionality added (see Section 4–3.4 “Power control” and
Section 26–6.6 “Alarm output”).
• Register containing device revision added (implemented starting with revision C, see
Section 30–9.11
).
• XTAL1 input selection and PCB layout guidelines added (see Section 4–2.2).
• Editorial updates throughout the user manual.
• ISP1302 replaces ISP1301 in Section 15–6.
• UART fractional baud rate generator disabled in auto baud mode (see Section 16–4.10
and Section 17–4.14).
03 20090115 LPC24XX user manual release.
Modifications:
Description of AHB1 and AHB2 configuration registers updated.
02 20081219 LPC24XX user manual release.
Modifications:
• Added parts LPC2420.
• Editorial updates.
• AHB1 and AHB2 configuration registers added.
01 20080718 Initial LPC24XX user manual release. Replaces all draft versions UM10237_1.00 to
UM10237_1.05.
UM10237_4 © NXP B.V. 2009. All rights reserved.
User manual Rev. 04 — 26 August 2009 3 of 792
1. Introduction
NXP Semiconductor designed the LPC2400 microcontrollers around a 16-bit/32-bit
ARM7TDMI-S CPU core with real-time debug interfaces that include both JTAG and
embedded Trace. The LPC2400 microcontrollers have 512 kB of on-chip high-speed
Flash memory. This Flash memory includes a special 128-bit wide memory interface and
accelerator architecture that enables the CPU to execute sequential instructions from
Flash memory at the maximum 72 MHz system clock rate. This feature is available only
on the LPC2000 ARM Microcontroller family of products. The LPC2400 can execute both
32-bit ARM and 16-bit Thumb instructions. Support for the two Instruction Sets means
Engineers can choose to optimize their application for either performance or code size at
the sub-routine level. When the core executes instructions in Thumb state it can reduce
code size by more than 30 % with only a small loss in performance while executing
instructions in ARM state maximizes core performance.
The LPC2400 microcontrollers are ideal for multi-purpose communication applications. It
incorporates a 10/100 Ethernet Media Access Controller (MAC), a USB full speed
device/host/OTG controller with 4 kB of endpoint RAM, four UARTs, two Controller Area
Network (CAN) channels, an SPI interface, two Synchronous Serial Ports (SSP), three I
2
C
interfaces, and an I
2
S interface. Supporting this collection of serial communications
interfaces are the following feature components; an on-chip 4 MHz internal precision
oscillator, 98 kB of total RAM consisting of 64 kB of local SRAM, 16 kB SRAM for
Ethernet, 16 kB SRAM for general purpose DMA, 2 kB of battery powered SRAM, and an
External Memory Controller (EMC). These features make this device optimally suited for
communication gateways and protocol converters. Complementing the many serial
communication controllers, versatile clocking capabilities, and memory features are
various 32-bit timers, an improved 10-bit ADC, 10-bit DAC, two PWM units, four external
interrupt pins, and up to 160 fast GPIO lines. The LPC2400 connect 64 of the GPIO pins
to the hardware based Vector Interrupt Controller (VIC) that means these external inputs
can generate edge-triggered, interrupts. All of these features make the LPC2400
particularly suitable for industrial control and medical systems.
2. How to read this manual
Important: The term “LPC24XX“ in this user manual will be used as a generic name for all
LPC2400 parts. It covers the following parts: LPC2458, LPC2420, LPC2460, LPC2468,
LPC2470, and LPC2478.
For information about individual parts refer to Table 1–1
and Table 1–2.
UM10237
Chapter 1: LPC24XX Introductory information
Rev. 04 — 26 August 2009 User manual
Table 1. LPC24XX overview
LPC2458 LPC2420/60 LPC2468 LPC2470 LPC2478
Features Section 1–3
Section 1–3 Section 1–3 Section 1–3 Section 1–3
Ordering options Section 1–5.1 Section 1–5.2 Section 1–5.3 Section 1–5.4 Section 1–5.5
Block diagrams Section 1–9 Section 1–10 Section 1–11 Section 1–12 Section 1–13
UM10237_4 © NXP B.V. 2009. All rights reserved.
User manual Rev. 04 — 26 August 2009 4 of 792
NXP Semiconductors
UM10237
Chapter 1: LPC24XX Introductory information
Most features and peripherals are identical for all LPC2400 parts. All differences are listed
in Table 1–2
.
3. LPC2400 features
• ARM7TDMI-S processor, running at up to 72 MHz.
• 98 kB on-chip SRAM includes:
– 64 kB of SRAM on the ARM local bus for high performance CPU access.
– 16 kB SRAM for Ethernet interface. Can also be used as general purpose SRAM.
– 16 kB SRAM for general purpose DMA use also accessible by the USB.
– 2 kB SRAM data storage powered from the RTC power domain.
• LPC2458/68/78 only: 512 kB on-chip Flash program memory with In-System
Programming (ISP) and In-Application Programming (IAP) capabilities. Flash program
memory is on the ARM local bus for high performance CPU access.
• Dual Advanced High-performance Bus (AHB) system allows memory access by
multiple resources and simultaneous program execution with no contention.
• EMC provides support for asynchronous static memory devices such as RAM, ROM
and Flash, as well as dynamic memories such as Single Data Rate SDRAM.
• Advanced Vectored Interrupt Controller (VIC), supporting up to 32 vectored interrupts.
• General Purpose AHB DMA controller (GPDMA) that can be used with the SSP, I
2
S,
and SD/MM interface as well as for memory-to-memory transfers.
• LPC2470/78 only: LCD controller, supporting both Super-Twisted Nematic (STN) and
Thin-Film Transistors (TFT) displays.
– Dedicated DMA controller.
– Selectable display resolution (up to 1024 × 768 pixels).
– Supports up to 24-bit true-color mode.
• Serial Interfaces:
– Ethernet MAC with MII/RMII interface and associated DMA controller. These
functions reside on an independent AHB bus.
– USB 2.0 full-speed dual port device/host/OTG controller with on-chip PHY and
associated DMA controller.
– Four UARTs with fractional baud rate generation, one with modem control I/O, one
with IrDA support, all with FIFO.
– CAN controller with two channels.
Table 2. Differences between LPC2400 parts
Pins/
High-speed
GPIO pins
Flash EMC LCD
LPC2458 180/136 512 kB 16-bit no
LPC2460/20 208/160 flashless 32-bit no
LPC2468 208/160 512 kB 32-bit no
LPC2470 208/160 flashless 32-bit yes
LPC2478 208/160 512 kB 32-bit yes
UM10237_4 © NXP B.V. 2009. All rights reserved.
User manual Rev. 04 — 26 August 2009 5 of 792
NXP Semiconductors
UM10237
Chapter 1: LPC24XX Introductory information
– SPI controller.
– Two SSP controllers, with FIFO and multi-protocol capabilities. One is an alternate
for the SPI port, sharing its interrupt. SSPs can be used with the GPDMA
controller.
– Three I
2
C-bus interfaces (one with open-drain and two with standard port pins).
– I
2
S (Inter-IC Sound) interface for digital audio input or output. It can be used with
the GPDMA.
• Other peripherals:
– SD/MMC memory card interface.
– 160 general purpose I/O pins with configurable pull-up/down resistors.
– 10-bit ADC with input multiplexing among 8 pins.
– 10-bit DAC.
– Four general purpose timers/counters with 8 capture inputs and 10 compare
outputs. Each timer block has an external count input.
– Two PWM/timer blocks with support for three-phase motor control. Each PWM has
an external count inputs.
– Real-Time Clock (RTC) with separate power domain, clock source can be the RTC
oscillator or the APB clock.
– 2 kB SRAM powered from the RTC power pin, allowing data to be stored when the
rest of the chip is powered off.
– WatchDog Timer (WDT). The WDT can be clocked from the internal RC oscillator,
the RTC oscillator, or the APB clock.
• Standard ARM test/debug interface for compatibility with existing tools.
• Emulation trace module supports real-time trace.
• Single 3.3 V power supply (3.0 V to 3.6 V).
• Four reduced power modes: idle, sleep, power-down, and deep power-down.
• Four external interrupt inputs configurable as edge/level sensitive. All pins on PORT0
and PORT2 can be used as edge sensitive interrupt sources.
• Processor wake-up from Power-down mode via any interrupt able to operate during
Power-down mode (includes external interrupts, RTC interrupt, USB activity, Ethernet
wake-up interrupt, CAN bus activity, PORT0/2 pin interrupt).
• Two independent power domains allow fine tuning of power consumption based on
needed features.
• Each peripheral has its own clock divider for further power saving. These dividers help
reducing active power by 20 - 30 %.
• Brownout detect with separate thresholds for interrupt and forced reset.
• On-chip power-on reset.
• On-chip crystal oscillator with an operating range of 1 MHz to 24 MHz.
• 4 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used as
the system clock. When used as the CPU clock, does not allow CAN and USB to run.
• On-chip PLL allows CPU operation up to the maximum CPU rate without the need for
a high frequency crystal. May be run from the main oscillator, the internal RC
oscillator, or the RTC oscillator.
