Serial RapidIO Gen2
Endpoint v4.1
LogiCORE IP Product Guide
Vivado Design Suite
PG007 June 7, 2017
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PG007 June 7, 2017
Table of Contents
IP Facts
Chapter 1: Overview
System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Unsupported Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Licensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Recommended Design Experience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Chapter 2: Product Specification
Standards Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Resource Utilization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Serial Transceiver Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Top-Level Wrapper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Port Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Register Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Chapter 3: Designing with the Core
General Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Shared Logic Related Port Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Protocol Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Chapter 4: Design Flow Steps
Customizing and Generating the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Constraining the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Synthesis and Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Chapter 5: Detailed Example Design
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
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Generating the Core. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Directory and File Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Example Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Implementing the Example Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Simulating the Example Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Chapter 6: Test Bench
Demonstration Test Bench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Appendix A: Packet and Control Symbol Formats
Scope. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Appendix B: Migrating and Upgrading
Migrating to the Vivado Design Suite. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Upgrading in the Vivado Design Suite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Appendix C: Debugging
Finding Help on Xilinx.com . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Debug Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Waveform Analysis and Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Hardware Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Appendix D: Additional Resources and Legal Notices
Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Please Read: Important Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
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Introduction
The LogiCORE™ IP Serial RapidIO Gen2
Endpoint Solution (SRIO Gen2 Endpoint)
comprises a highly flexible and optimized Serial
RapidIO Gen2 Physical Layer and a Serial
RapidIO Gen2 Logical (I/O) and Transport Layer.
This IP solution is provided in netlist form with
supporting example design code. The SRIO
Gen2 Endpoint supports 1x, 2x, and 4x lane
widths. It comes with a configurable buffer
design, reference clock module, reset module,
and configuration fabric reference design. The
SRIO Gen2 Endpoint uses AXI4-Stream
interfaces for high-throughput data transfer
and AXI4-Lite interfaces for the configuration
(maintenance) interfaces.
Features
•Designed to
RapidIO Interconnect
Specification rev. 2.2
• Supports 1x, 2x and 4x operation with the
ability to train down to 1x from 2x or 4x
• Supports per-lane speeds of 1.25, 2.5,
3.125, 5.0, and 6.25 Gbaud
Logical Layer
• Concurrent Initiator and Target operations
• Doorbell and Message support
• Dedicated port for maintenance
transactions
• Simple handshaking mechanism to control
data flow using standard AXI4-Lite and
AXI4-Stream interfaces
• Programmable source ID on all outgoing
packets
• Optional large system support for 16-bit
device IDs
Buff
er
•I
ndependently configurable TX and RX Buffer
depths of 8, 16, or 32 packets
• Support for independent clocks
•
Optional TX Flow C
ontrol support
Physical Layer
• Configurable IDLE1/IDLE2 sequence
support
•Su
pports critical request flow
• Support for multicast events
IP Facts
LogiCORE IP Facts Table
Core Specifics
Supported Device
Family
(1)
1. For a complete list of supported devices, see the Vivado IP
catalog.
UltraScale+™ Families,
UltraScale™ Architecture, Zynq®-7000,
Virtex®-7, Kintex®-7, Artix®-7
Supported User
Interfaces
AXI4-Stream, AXI4-Lite
Resources
Performance and Resource Utilization web
page
Provided with Core
Design Files Encrypted RTL
Example Design
Configuration Fabric Design
with Verilog Source
Test Bench Verilog
Constraints File XDC
Simulation Model Encrypted Verilog
Supported S/W
Driver
N/A
Tested Design Flows
(2)
2. For the supported versions of the tools, see the
Xilinx Design Tools: Release Notes Guide.
Design Entry Vivado® Design Suite
Simulation
(3)
3. Requires a Verilog LRM-IEEE 1364-2005 encryption-compliant
simulator.
For the supported simulators, see the Xilinx
Design Tools: Release Notes Guide
Synthesis Vivado synthesis
Support
Provided by Xilinx at the Xilinx Support web page
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Chapter 1
Overview
The RapidIO Interconnect Architecture, designed to be compatible with the most popular
integrated communications processors, host processors, and networking digital signal
processors, is a high-performance, packet-switched, interconnect technology. It addresses
the need of the high-performance embedded industry for reliability, increased bandwidth,
and faster bus speeds in an intra-system interconnect.
The RapidIO standard is defined in three layers: logical, transport and physical. The logical
layer defines the overall protocol and packet formats. This is the information necessary for
endpoints to initiate and complete a transaction. The transport layer provides the route
information necessary for a packet to move from endpoint to endpoint. The physical layer
describes the device-level interface specifics such as packet transport mechanisms, flow
control, electrical characteristics, and low-level error management. This partitioning
provides the flexibility to add new transaction types to the logical specification without
requiring modification to the transport or physical layer specifications.
• For more information about the RapidIO core, see www.xilinx.com/rapidio
• For more information about the RapidIO standards and specifications, see
www.rapidio.org
System Overview
The SRIO Gen2 Endpoint is comprised of the following:
• A Serial RapidIO Gen2 top-level wrapper (srio_gen2_<core_version>_unifiedtop)
containing:
°
Serial RapidIO Gen2 Physical Layer (PHY)
°
Serial RapidIO Gen2 Logical (I/O) and Transport Layer (LOG)
°
Serial RapidIO Gen2 Buffer Design (BUF)
• Reference design for clocking, resets, and configuration accesses
The SRIO Gen2 Endpoint is shown in Figure 1-1.
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