VHDL 8X8点阵 心形可移动 调试通过

--**************库定义、 包定义********************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity led_array is
port(
    clk : in std_logic;
    led : out std_logic_vector(7 downto 0);
    z1  : out std_logic_vector(7 downto 0)
);
end led_array;
architecture led of led_array is
signal clk_1K : std_logic;
signal clk_1k_count : std_logic_vector(15 downto 0);
signal z1_en : integer range 0 to 7;
signal clk_2Hz_count : std_logic_vector(24 downto 0);
signal led_temp : std_logic_vector(7 downto 0);
signal clk_2Hz : integer range 0 to 7;
begin
process(clk)--1KHz
begin
if clk'event and clk='1' then
    clk_1k_count<=clk_1k_count+'1';
    clk_1K<='0';
    if clk_1k_count>=x"c350" then 
       clk_1K<='1';
       clk_1k_count<=x"0000";
     end if;