FPGA实现序列检测器两种实现方式（状态机+移位寄存器）

Release 14.7 - par P.20131013 (nt) Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. Mon Oct 23 19:47:01 2017 INFO: The IO information is provided in three file formats as part of the Place and Route (PAR) process. These formats are: 1. The <design name>_pad.txt file (this file) designed to provide information on IO usage in a human readable ASCII text format viewable through common text editors. 2. The <design namd>_pad.csv file for use with spreadsheet programs such as MS Excel. This file can also be read by PACE to communicate post PAR IO information. 3. The <design name>.pad file designed for parsing by customers. It uses the "|" as a data field separator. INPUT FILE: top_map.ncd OUTPUT FILE: top_pad.txt PART TYPE: xc3s100e SPEED GRADE: -5 PACKAGE: cp132 Pinout by Pin Number: +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |Pin Number|Signal Name|Pin Usage|Pin Name |Direction|IO Standard|IO Bank Number|Drive (mA)|Slew Rate|Termination|IOB Delay|Voltage |Constraint|IO Register|Signal Integrity| +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |A1 | | |PROG_B | | | | | | | | | | | | |A2 | | |TDI | | | | | | | | | | | | |A3 | |DIFFM |IO_L11P_0 |UNUSED | |0 | | | | | | | | | |A4 | | |NC | | | | | | | | | | | | |A5 | | |VCCAUX | | | | | | | |2.5 | | | | |A6 | | |VCCO_0 | | |0 | | | | |2.50 | | | | |A7 | |DIFFM |IO_L07P_0/GCLK10 |UNUSED | |0 | | | | | | | | | |A8 | | |GND | | | | | | | | | | | | |A9 | |DIFFS |IO_L05N_0/GCLK7 |UNUSED | |0 | | | | | | | | | |A10 | |DIFFM |IO_L04P_0/GCLK4 |UNUSED | |0 | | | | | | | | | |A11 | | |VCCINT | | | | | | | |1.2 | | | | |A12 | | |NC | | | | | | | | | | | | |A13 | |DIFFM |IO_L01P_0 |UNUSED | |0 | | | | | | | | | |A14 | | |TDO | | | | | | | | | | | | |B1 |ps2clk |IBUF |IO_L01N_3 |INPUT |LVCMOS25* |3 | | | |NONE | |LOCATED |NO |NONE | |B2 | |DIFFM |IO_L01P_3 |UNUSED | |3 | | | | | | | | | |B3 | |DIFFS |IO_L11N_0/HSWAP |UNUSED | |0 | | | | | | | | | |B4 | |IBUF |IP |UNUSED | |0 | | | | | | | | | |B5 | |DIFFM |IO_L09P_0 |UNUSED | |0 | | | | | | | | | |B6 | |DIFFM |IO_L08P_0 |UNUSED | |0 | | | | | | | | | |B7 | |DIFFS |IO_L07N_0/GCLK11 |UNUSED | |0 | | | | | | | | | |B8 |clk |IBUF |IP_L06P_0/GCLK8 |INPUT |LVCMOS25* |0 | | | |NONE | |LOCATED |NO |NONE | |B9 | |DIFFM |IO_L05P_0/GCLK6 |UNUSED | |0 | | | | | | | | | |B10 | | |VCCO_0 | | |0 | | | | |2.50 | | | | |B11 | | |NC | | | | | | | | | | | | |B12 | | |NC | | | | | | | | | | | | |B13 | | |TCK | | | | | | | | | | | | |B14 | | |TMS | | | | | | | | | | | | |C1 | | |NC | | | | | | | | | | | | |C2 | |DIFFS |IO_L02N_3 |UNUSED | |3 | | | | | | | | | |C3 |ps2sda |IBUF |IO_L02P_3 |INPUT |LVCMOS25* |3 | | | |NONE | |LOCATED |NO |NONE | |C4 | | |NC | | | | | | | | | | | | |C5 | |DIFFS |IO_L09N_0 |UNUSED | |0 | | | | | | | | | |C6 | |DIFFS |IO_L08N_0/VREF_0 |UNUSED | |0 | | | | | | | | | |C7 | | |GND | | |