STM8L15x的LCD调试实验（显示实现按键切换）

/** ****************************************************************************** * @file stm8l15x_clk.c * @author MCD Application Team * @version V1.4.0 * @date 09/24/2010 * @brief This file provides all the CLK firmware functions. ****************************************************************************** * @copy * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2> */ /* Includes ------------------------------------------------------------------*/ #include "stm8l15x_clk.h" /** @addtogroup STM8L15x_StdPeriph_Driver * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /* Private Variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** * @addtogroup CLK_Private_Constants * @{ */ __CONST uint8_t SYSDivFactor[5] = { 1, 2, 4, 8, 16 } ; /*!< Holds the different Master clock Divider factors */ /** * @} */ /** * @addtogroup CLK_Public_Functions * @{ */ /** * @brief Deinitializes the CLK peripheral registers to their default reset values. * @param None * @retval None */ void CLK_DeInit(void) { CLK->ICKCR = CLK_ICKCR_RESET_VALUE; CLK->ECKCR = CLK_ECKCR_RESET_VALUE; CLK->CRTCR = CLK_CRTCR_RESET_VALUE; CLK->CBEEPR = CLK_CBEEPR_RESET_VALUE; CLK->SWR = CLK_SWR_RESET_VALUE; CLK->SWCR = CLK_SWCR_RESET_VALUE; CLK->CKDIVR = CLK_CKDIVR_RESET_VALUE; CLK->PCKENR1 = CLK_PCKENR1_RESET_VALUE; CLK->PCKENR2 = CLK_PCKENR2_RESET_VALUE; CLK->PCKENR3 = CLK_PCKENR3_RESET_VALUE; CLK->CSSR = CLK_CSSR_RESET_VALUE; CLK->CCOR = CLK_CCOR_RESET_VALUE; CLK->HSITRIMR = CLK_HSITRIMR_RESET_VALUE; CLK->HSICALR = CLK_HSICALR_RESET_VALUE; CLK->HSIUNLCKR = CLK_HSIUNLCKR_RESET_VALUE; CLK->REGCSR = CLK_REGCSR_RESET_VALUE; } /** * @brief Enables or disables the Internal High Speed oscillator (HSI). * @param NewState : new state of HSI, value accepted ENABLE, DISABLE. * @retval None */ void CLK_HSICmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Set HSION bit */ CLK->ICKCR |= CLK_ICKCR_HSION; } else { /* Reset HSION bit */ CLK->ICKCR &= (uint8_t)(~CLK_ICKCR_HSION); } } /** * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value. * @param CLK_HSICalibrationValue : calibration trimming value. * @retval None */ void CLK_AdjustHSICalibrationValue(uint8_t CLK_HSICalibrationValue) { /* two consecutive write access to HSIUNLCKR register to unlock HSITRIMR */ CLK->HSIUNLCKR = 0xAC; CLK->HSIUNLCKR = 0x35; /* Store the new value */ CLK->HSITRIMR = (uint8_t)CLK_HSICalibrationValue; } /** * @brief Enables or disables the Internal Low Speed oscillator (LSI). * @param NewState : new state of LSI, value accepted ENABLE, DISABLE. * @retval None */ void CLK_LSICmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Set LSION bit */ CLK->ICKCR |= CLK_ICKCR_LSION; } else { /* Reset LSION bit */ CLK->ICKCR &= (uint8_t)(~CLK_ICKCR_LSION); } } /** * @brief Configures the HSE Clock source. * @note In case of Enabling HSE Bypass be sure * that SWI, CKM and Clock RTC are not using HSE as clock source * @param CLK_HSE : This parameter specifies the HSE clock configuarton. * This parameter can be a value of @ref CLK_HSE_TypeDef. * @retval None */ void CLK_HSEConfig(CLK_HSE_TypeDef CLK_HSE) { /* Check the parameters */ assert_param(IS_CLK_HSE(CLK_HSE)); /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/ /* Reset HSEON bit */ CLK->ECKCR &= (uint8_t)~CLK_ECKCR_HSEON; /* Reset HSEBYP bit */ CLK->ECKCR &= (uint8_t)~CLK_ECKCR_HSEBYP; /* Configure HSE */ CLK->ECKCR |= (uint8_t)CLK_HSE; } /** * @brief Configures the LSE Clock source. * @note In case of Enabling LSE ByPass be sure that SWI, CKM * and Clock RTC are not using LSE as clock source * @param CLK_LSE : This parameter specifies the LSE clock configuarton. * This parameter can be a value of @ref CLK_ConfigLSE_TypeDef. * @retval None */ void CLK_LSEConfig(CLK_LSE_TypeDef CLK_LSE) { /* Check the parameters */ assert_param(IS_CLK_LSE(CLK_LSE)); /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/ /* Reset LSEON bit */ CLK->ECKCR &= (uint8_t)~CLK_ECKCR_LSEON; /* Reset LSEBYP bit */ CLK->ECKCR &= (uint8_t)~CLK_ECKCR_LSEBYP; /* Configure LSE */ CLK->ECKCR |= (uint8_t)CLK_LSE; } /** * @brief Configures the System clock (SYSCLK) source. * @param CLK_SYSCLKSource : Specifies the new clock. * This parameter can be a value of @ref CLK_SYSCLKSource_TypeDef. * @retval None */ void CLK_SYSCLKSourceConfig(CLK_SYSCLKSource_TypeDef CLK_SYSCLKSource) { /* check teh parameters */ assert_param(IS_CLK_SOURCE(CLK_SYSCLKSource)); /* Selection of the target clock source */ CLK->SWR = (uint8_t)CLK_SYSCLKSource; } /** * @brief Configures the System clock (SYSCLK) dividers. * @param CLK_SYSCLKDiv : Specifies the system clock divider to apply. * This parameter can be a value of @ref CLK_SYSCLKDiv_TypeDef. * @retval None */ void CLK_SYSCLKDivConfig(CLK_SYSCLKDiv_TypeDef CLK_SYSCLKDiv) { /* check the parameters */ assert_param(IS_CLK_SYSTEM_DIVIDER(CLK_SYSCLKDiv)); CLK->CKDIVR = (uint8_t)(CLK_SYSCLKDiv); } /** * @brief Enables or disables the clock switch execution. * @param NewState : new state of clock switch, value accepted ENABLE, DISABLE. * @retval None */ void CLK_SYSCLKSourceSwitchCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Set SWEN bit */ CLK->SWCR |= CLK_SWCR_SWEN; } else { /* Reset SWEN bit */ CLK->SWCR &= (uint8_t)(~CLK_SWCR_SWEN); } } /** * @brief Returns the clock source used as system clock. * @param None * @retval Clock used as System clock (SYSCLK) source. * The returned value can be one of the following: * - CLK_SYSCLKSource_HSI: HSI used as system clock * - CLK_SYSCLKSource_LSI: LSI used as system clock * - CLK_SYSCLKSource_HSE: HSE used as system clock * - CLK_SYSCLKSource_LSE: LSE used as system clock */ CLK_SYSCLKSource_TypeDef CLK_GetSYSCLKSource(void) { return ((CLK_SYSCLKSource_TypeDef)(CLK->SCSR)); } /** * @brief Enables the Clock Security System. * @note Once CSS is enabled it cannot be disabled until the next reset. * @param None * @retval None */ void CLK_ClockSecuritySystemEnable(void) { /* Set CSSEN bit */ CLK->CSSR |= CLK_CSSR_CSSEN; } /** * @brief Enables the Clock Security System deglitcher system. * @param None * @retval None */ void CLK_ClockSecuritySytemDeglitchCmd(FunctionalState NewState