Fundamentals of PCB Layout Guidelines for radioOne® Designs Application Note Contents
80-V9813-1 Rev. A 4 QUALCOMM Proprietary
Figures
Figure 2-1 Example parts placement and conceptual signal flow................................................. 11
Figure 2-2 Shield partitioning....................................................................................................... 12
Figure 2-3 Shield mounting and wall cutout for microstrip traces ............................................... 13
Figure 2-4 Shielding effectiveness – measured sensitivity performance...................................... 14
Figure 3-1 Example stack-ups (six and eight layers).................................................................... 16
Figure 3-2 Microstrip and stripline transmission lines ................................................................. 18
Figure 3-3 Ground vias improve coplanar isolation (stripline, top view)..................................... 22
Figure 3-4 Ground vias improve coplanar isolation (cross-section view) .................................... 22
Figure 3-5 Recommended 32 QFN land pattern........................................................................... 24
Figure 3-6 Recommended 32 QFN stencil pattern ....................................................................... 24
Figure 4-1 Design example – MSM6025™ with Cellular-CDMA CMOS RF Chipset ............... 26
Figure 4-2 Example layer 1 – RFIC section ................................................................................. 28
Figure 4-3 Example layer 2 – RFIC section ................................................................................. 29
Figure 4-4 Example layer 2 under MSM device........................................................................... 30
Figure 4-5 Example layer 3 – RFIC section ................................................................................. 31
Figure 4-6 Example layers 3 and 5 – digital section..................................................................... 31
Figure 4-7 Example layer 4 – RFIC section ................................................................................. 32
Figure 4-8 Example layer 6 – display and keypad connections.................................................... 33
Figure 5-1 Parasitic capacitance between layers........................................................................... 36
Figure 5-2 Stripline routing of RF front-end connections (layer 3 shown) .................................. 37
Figure 5-3 RFR6122 LNA input matching network..................................................................... 38
Figure 5-4 RFR6122 LNA output matching network................................................................... 38
Figure 5-5 RFR6122 downconverter input matching network ..................................................... 39
Figure 5-6 Routing high-level and sensitive traces (layer 3 shown)............................................. 40
Figure 5-7 Exposed SBI lines cause radiated desensitization....................................................... 45
Figure 5-8 Examples of good and bad PA power supply routing................................................. 47
Figure 5-9 Example of poor RFT power supply routing (layer 2 shown) .................................... 48
Figure 6-1 Example radiated sensitivity improvement ................................................................. 51
Figure 6-2 SBI traces corrupting the TCXO signals..................................................................... 51
Figure 6-3 Proper routing of SBI and TCXO signals at PMIC..................................................... 52
Figure 6-4 Final reference design sensitivity test results.............................................................. 53
Tables
Table 1-1 RF chipset documentation .............................................................................................. 7
Table 3-1 Recommended layer assignments (8-layer board)........................................................ 17
Table 3-2 Recommended layer assignments (6-layer board)........................................................ 17
Table 3-3 Example microstrip design for a 6-layer board ............................................................ 19
Table 3-4 Example stripline design for a 6-layer board................................................................ 20
Table 7-1 Layout checklist............................................................................................................ 56
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