################################################################################
# Vivado (TM) v2018.3 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required
# to simulate the design for a simulator, the directory structure
# and the generated exported files.
#
################################################################################
1. Simulate Design
To simulate design, cd to the simulator directory and execute the script.
For example:-
% cd questa
% ./top.sh
The export simulation flow requires the Xilinx pre-compiled simulation library
components for the target simulator. These components are referred using the
'-lib_map_path' switch. If this switch is specified, then the export simulation
will automatically set this library path in the generated script and update,
copy the simulator setup file(s) in the exported directory.
If '-lib_map_path' is not specified, then the pre-compiled simulation library
information will not be included in the exported scripts and that may cause
simulation errors when running this script. Alternatively, you can provide the
library information using this switch while executing the generated script.
For example:-
% ./top.sh -lib_map_path /design/questa/clibs
Please refer to the generated script header 'Prerequisite' section for more details.
2. Directory Structure
By default, if the -directory switch is not specified, export_simulation will
create the following directory structure:-
<current_working_directory>/export_sim/<simulator>
For example, if the current working directory is /tmp/test, export_simulation
will create the following directory path:-
/tmp/test/export_sim/questa
If -directory switch is specified, export_simulation will create a simulator
sub-directory under the specified directory path.
For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
command will create the following directory:-
/tmp/test/my_test_area/func_sim/questa
By default, if -simulator is not specified, export_simulation will create a
simulator sub-directory for each simulator and export the files for each simulator
in this sub-directory respectively.
IMPORTANT: Please note that the simulation library path must be specified manually
in the generated script for the respective simulator. Please refer to the generated
script header 'Prerequisite' section for more details.
3. Exported script and files
Export simulation will create the driver shell script, setup files and copy the
design sources in the output directory path.
By default, when the -script_name switch is not specified, export_simulation will
create the following script name:-
<simulation_top>.sh (Unix)
When exporting the files for an IP using the -of_objects switch, export_simulation
will create the following script name:-
<ip-name>.sh (Unix)
Export simulation will create the setup files for the target simulator specified
with the -simulator switch.
For example, if the target simulator is "ies", export_simulation will create the
'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
file.
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verilog hdl编写的FPGA驱动AD9516时钟芯片的案例代码,包含SPI的驱动代码 实现AD9516时钟芯片的配置,可根据使用例程修改项目需要的时钟配置,可直接使用。
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AD9516-cfg-demo(verilog hdl编写的FPGA驱动AD9516时钟芯片的案例代码) (409个子文件)
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
runme.bat 268B
runme.bat 229B
runme.bat 229B
runme.bat 229B
top.bit 16.61MB
top.bit 16.61MB
top_routed.dcp 1.74MB
top_placed.dcp 1.56MB
top_opt.dcp 1.15MB
ila_0.dcp 523KB
ila_0.dcp 523KB
ila_0.dcp 521KB
dbg_hub.dcp 347KB
top.dcp 31KB
clk_wiz_0.dcp 10KB
clk_wiz_0.dcp 10KB
clk_wiz_0.dcp 10KB
clk_wiz_0.dcp 10KB
compile.do 750B
compile.do 726B
compile.do 685B
compile.do 679B
compile.do 675B
compile.do 655B
compile.do 614B
compile.do 604B
simulate.do 311B
simulate.do 306B
simulate.do 306B
simulate.do 303B
simulate.do 294B
simulate.do 294B
simulate.do 195B
simulate.do 187B
elaborate.do 183B
elaborate.do 175B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
simulate.do 11B
simulate.do 11B
run.f 466B
run.f 457B
run.f 450B
run.f 441B
usage_statistics_webtalk.html 157KB
hw_ila_data_3.ila 269KB
xsim.ini 22KB
xsim.ini 22KB
vivado.jou 767B
vivado.jou 766B
vivado.jou 761B
vivado.jou 757B
ISEWrap.js 7KB
ISEWrap.js 7KB
ISEWrap.js 7KB
ISEWrap.js 7KB
rundef.js 1KB
rundef.js 1KB
rundef.js 1KB
rundef.js 1KB
hw_ila_3.layout 247KB
runme.log 106KB
runme.log 35KB
runme.log 24KB
runme.log 24KB
project_1.lpr 343B
top.ltx 2KB
debug_nets.ltx 2KB
top.ltx 2KB
elab.opt 188B
elab.opt 180B
vivado.pb 172KB
vivado.pb 38KB
vivado.pb 37KB
place_design.pb 17KB
route_design.pb 15KB
opt_design.pb 15KB
write_bitstream.pb 7KB
init_design.pb 6KB
messagePromote.pb 2KB
top_power_summary_routed.pb 728B
ila_0_utilization_synth.pb 289B
clk_wiz_0_utilization_synth.pb 289B
top_utilization_placed.pb 289B
top_utilization_synth.pb 289B
vivado.pb 149B
top_timing_summary_routed.pb 109B
top_drc_routed.pb 75B
top_methodology_drc_routed.pb 52B
top_route_status.pb 44B
top_drc_opted.pb 37B
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