Understanding Clock Domain Crossing Issues
By Saurabh Verma, Ashima S.
Dabare, Atrenta
Introduction
SoCs are becoming more complex these days. A lot of functionality is being added to chips
and data is frequently transferred from one clock domain to another. Hence, clock domain
crossing verification has become one of the major verification challenges in deep submicron
designs.
A clock domain crossing occurs whenever data is transferred from a flop driven by one clock
to a flop driven by another clock.
1. Clock domain crossing.
In Figure 1, signal A is launched by the C1 clock domain and needs to be captured properly
by the C2 clock domain. Depending on the relationship between the two clocks, there could
be different types of problems in transferring data from the source clock to the destination
clock. Along with that, the solutions to those problems can also be different.
Traditional methods like simulation and static timing analysis alone are not sufficient to verify
that the data is transferred consistently and reliably across clock domains. Hence, new
verification methodologies are required, but before devising a new methodology it is important
to understand the issues related to clock domain crossings properly. Different types of clock
domain crossings are discussed here along with the possible issues encountered in each one
of them and their solutions. A new verification methodology is then proposed which will
ensure that data is transferred correctly across clock domains.
In all the subsequent sections, the signal names shown in Figure 1 are directly used. For
example, C1 and C2 imply the source and destination clocks respectively. Similarly A and B
are used as source and destination flop outputs respectively. Also, the source and destination
flops are assumed to be positive edge triggered.
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