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Computer Systems

Architecture

A Networking Approach

Second Edition

Rob Williams

WillaFMv3.qxd 11/30/07 10:15 AM Page iii

Functional units and the fetch–execute cycle 47

3.1 The naming of parts – CPU, memory, IO units 48

3.2 The CPU fetch–execute cycle – high-speed tedium 52

3.3 System bus – synchronous or asynchronous? 56

3.4 System clock – instruction cycle timing 59

3.5 Pre-fetching – early efforts to speed things up 61

3.6 Memory length – address width 63

3.7 Endian-ness – Microsoft vs. Unix, or Intel vs. Motorola? 65

3.8 Simple input–output – parallel ports 67

Building computers from logic: the control unit 73

4.1 Electronic Lego and logic – the advantage of modular units 74

4.2 Basic logic gates – truth tables for AND, OR, XOR and NOT 75

4.3 Truth tables and multiplexers – a simple but effective design tool 77

4.4 Programmable logic – reconfigurable logic chips 79

4.5 Traffic light controllers – impossible to avoid! 82

4.6 Circuit implementation from truth tables – some practical tips 83

4.7 Decoder logic – essential for control units and memories 85

4.8 CPU control unit – the ‘brain’ 87

4.9 Washing machine controllers – a simple CU 88

4.10 RISC vs. CISC decoding – in search of faster computers 91

Building computers from logic: the ALU 97

5.1 De Morgan’s equivalences – logical interchangeability 98

5.2 Binary addition – half adders, full adders, parallel adders 98

5.3 Binary subtraction – using two’s complement integer format 101

5.4 Binary shifting – barrel shifter 103

5.5 Integer multiplication – shifting and adding 105

5.6 Floating-point numbers – from very, very large to very, very small 108

Building computers from logic: the memory 117

6.1 Data storage – one bit at a time 118

6.2 Memory devices – memory modules for computers 120

6.3 Static memory – a lot of fast flip-flops 121

6.4 Dynamic memory – a touch of analogue amid the digital 122

6.5 DRAM refreshing – something else to do 124

6.6 Page access memories – EDO and SDRAM 124

6.7 Memory mapping – addressing and decoding 127

6.8 IO port mapping – integration vs. differentiation 131

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WillaFMv3.qxd 11/28/07 9:18 AM Page vi

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redkaoliang

2018-02-24

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