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I2C

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i2c_master_slave_core.tar.gz （70个子文件）

i2c_master_slave_core

verilog

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Repository 52B

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rtl

ms_core.v 29KB

i2c_blk.v 5KB

counter.v 1KB

shift.v 2KB

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Repository 56B

Entries 243B

controller_interface.v 12KB

doc

i2c_spec.doc 558KB

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i2c_spec.pdf 816KB

i2c_master_slave_core

verilog

CVS

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Repository 74B

Entries 10B

rtl

ms_core.v 29KB

i2c_blk.v 5KB

counter.v 1KB

shift.v 2KB

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Entries 243B

controller_interface.v 12KB

svtb

vmm_svtb

vmm_clkgen.sv 634B

vmm_i2c_scenario_generator.sv 6KB

vmm_i2c_callback.sv 473B

vmm_i2c_scenario_packet.sv 2KB

vmm_i2c_slave_driver.sv 20KB

vmm_i2c_data_packet.sv 1KB

vmm_i2c_stimulus_packet.sv 3KB

vmm_i2c_interface.sv 2KB

vmm_program_test.sv 764B

vmm_i2c_driver.sv 27KB

sb_callback.sv 3KB

vmm_i2c_env.sv 5KB

config.sv 808B

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vmm_i2c_coverage.sv 6KB

vmm_i2c_monitor.sv 6KB

vmm_program1_test.sv 4KB

vmm_i2c_mon_pkt.sv 2KB

vmm_i2c_scoreboard.sv 7KB

vmm_i2c_sb_pkt.sv 1KB

vmm_i2c_top.sv 2KB

vmm_i2c_reg_pkt.sv 1KB

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Readme 627B

doc

i2c_core_verification_plan.pdf 298KB

i2c_spec.doc 558KB

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i2c_spec.pdf 816KB

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I2C-Master / Slave Core Specification

Authors

TooMuch Semiconductor Solutions (info@toomuchsemi.com)

Revision No.

1.0

Disclaimer

This source file may be used and distributed without restriction .

This software is provided “as is” and without any express or implied warranties, including, but not limited to, the

implied warranties of merchantability and fitness for a particular purpose. in no event shall the author or

contributors be liable for any direct, indirect, incidental, special, exemplary, or consequential damages (including,

but not limited to, procurement of substitute goods or services; loss of use, data, or profits; or business

interruption) however caused and on any theory of liability, whether in contract, strict liability, or tort (including

negligence or otherwise) arising in any way out of the use of this software, even if advised of the possibility of

such damage.

Introduction

C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange between

devices. It is most suitable for applications requiring occasional communication over a short distance between

many devices.

Devices controlling the buses are called as Master. Master is responsible for generation of bus control and

synchronizing signals. Slaves just follow the Master. Any I

C device can be either receiver or transmitter. The I

standard is a true multi-master bus including collision detection and arbitration that prevents data corruption if two

or more masters attempt to control the bus simultaneously.

Design implementation

This design serves both as I

C compatible master and slave. It has two state machines,first is the main state

machine which is same for either master or slave , while second is responsible for generating clock signal in

master mode. These state machines have been interface with a module which is used for decoding the commands

from processor. On top of these, a module has been created which actually interfaces with the processor. The

communication between design and processor follow the Wishbone protocol.

This Design supports the following functionalities:

 Both Master and slave operation

 Both Interrupt and non interrupt data-transfers

 Start/Stop/Repeated Start generation

 Fully supports arbitration process

 Software programmable acknowledge bit

 Software programmable time out feature

 programmable address register

 Programmable SCL frequency

 Soft reset of I2C Master/Salve

 Programmable maximum SCL low period

 synthesis core

Limitation

Design does not support clock stretching .

Pin Interfaces

Processor interface signals

Port Width Direction Description

clk 1 input system clock

reset 1 input system reset

add_bus [7:0] input processor address bus

data_bus [7:0] inout processor data bus

as 1 input When asserted indicates address

present on bus is valid.

ds 1 input When asserted indicates data on data

bus is valid

rw 1 input “1” indicates read,”0” indicates

write,from processor side.

irq 1 output interrupt bit for processor

I2C connections

Port Width Direction Description

SCL_oe 1 out Serial Clock enable line

SCL_o 1 out Serial clock line output

SCL_In

1 In Serial clock input line

SDA_oe

1 Out Serial data enable line

SDA_o

1 Out Serial data output line

SDA_In

1 In Serial data input line

Registers Implemented

Name Width Access Description

PRER 8 RW Clock Prescale register

CTR 8 RW Control register

SR 8 R Status register

TO 8 W Time out Register

ADDR

W Address Register

DTR

RW Data Transmit Register

DRR

R Data Receive Register

Pre-scale Register

This register is used to prescale the SCL clock line. Due to the structure of the I

C interface, the core uses a

4*SCL clock internally. The prescale register must be programmed to this 4*SCL bit rate. This is used for

programming the SCL frequency.

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pengyu2006jnu

2020-06-23

不错，比较有参考价值。

u013533352

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