Volume II: RISC-V Privileged Architectures V20190608-Priv-MSU-Ratified iii
Preface to Version 1.10
This is version 1.10 of the RISC-V privileged architecture proposal. Changes from version 1.9.1
include:
• The previous version of this document was released under a Creative Commons Attribution
4.0 International License by the original authors, and this and future versions of this document
will be released under the same license.
• The explicit convention on shadow CSR addresses has been removed to reclaim CSR space.
Shadow CSRs can still be added as needed.
• The mvendorid register now contains the JEDEC code of the core provider as opposed to
a code supplied by the Foundation. This avoids redundancy and offloads work from the
Foundation.
• The interrupt-enable stack discipline has been simplified.
• An optional mechanism to change the base ISA used by supervisor and user modes has been
added to the mstatus CSR, and the field previously called Base in misa has been renamed
to MXL for consistency.
• Clarified expected use of XS to summarize additional extension state status fields in mstatus.
• Optional vectored interrupt support has been added to the mtvec and stvec CSRs.
• The SEIP and UEIP bits in the mip CSR have been redefined to support software injection
of external interrupts.
• The mbadaddr register has been subsumed by a more general mtval register that can now
capture bad instruction bits on an illegal instruction fault to speed instruction emulation.
• The machine-mode base-and-bounds translation and protection schemes have been removed
from the specification as part of moving the virtual memory configuration to sptbr (now
satp). Some of the motivation for the base and bound schemes are now covered by the PMP
registers, but space remains available in mstatus to add these back at a later date if deemed
useful.
• In systems with only M-mode, or with both M-mode and U-mode but without U-mode
trap support, the medeleg and mideleg registers now do not exist, whereas previously they
returned zero.
• Virtual-memory page faults now have mcause values distinct from physical-memory access
exceptions. Page-fault exceptions can now be delegated to S-mode without delegating excep-
tions generated by PMA and PMP checks.
• An optional physical-memory protection (PMP) scheme has been proposed.
• The supervisor virtual memory configuration has been moved from the mstatus register to
the sptbr register. Accordingly, the sptbr register has been renamed to satp (Supervisor
Address Translation and Protection) to reflect its broadened role.
• The SFENCE.VM instruction has been removed in favor of the improved SFENCE.VMA
instruction.
• The mstatus bit MXR has been exposed to S-mode via sstatus.
• The polarity of the PUM bit in sstatus has been inverted to shorten code sequences involving
MXR. The bit has been renamed to SUM.
• Hardware management of page-table entry Accessed and Dirty bits has been made optional;
simpler implementations may trap to software to set them.
