一个简单的100进位计数器

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;


entity cuont is
    Port ( clk : in  STD_LOGIC;
           rst : in  STD_LOGIC;
           y : out  STD_LOGIC_VECTOR (7 downto 0));
end cuont;

architecture Behavioral of cuont is
signal y1: std_logic_vector (7 downto 0);
begin

 
  process(clk,rst)
   
  begin
     if(rst='0') then
    y1 <="01011001";
    elsif (clk'event and clk ='1') then
       if(y1(7 downto 0) ="00000000") then
  y1 <="01011001";
 elsif(y1(3 downto 0)="0000") then
 y1 <= y1-7;
        else  y1 <= y1-1;

      end if;
  end if;