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### DSP的文档资料知识点概述 #### 一、TMS320F2833x与TMS320F2823x系列DSCs特性与功能介绍 ##### 1.1 特性 - **高性能处理器**: TMS320F2833x 和 TMS320F2823x 系列数字信号控制器 (DSCs) 集成了C28x CPU，提供高速处理能力。 - **丰富的内存资源**: 包括多种类型的SRAM以及Boot ROM等。 - **外设接口**: 提供了多个高级外设模块，如增强型PWM模块、高分辨率PWM模块、ADC模块等。 - **低功耗模式**: 支持多种低功耗模式，以适应不同应用场景的需求。 ##### 1.2 入门指南 - **开发环境**: 推荐使用TI提供的集成开发环境 (IDE) 和相关工具链进行开发。 - **硬件资源**: 选择合适的评估板或开发套件进行实际操作和测试。 - **软件支持**: 利用提供的代码示例和参考设计快速上手。 #### 二、引脚分配与信号描述 ##### 2.1 引脚分配 - **控制引脚**: 包括复位、时钟输入等关键控制信号。 - **数据总线**: 定义了与外部存储器或其他设备的数据交换方式。 - **地址总线**: 用于寻址外部存储器或外设的地址信号。 - **中断引脚**: 外部中断请求输入。 - **GPIO**: 通用输入/输出端口，可用于自定义应用需求。 ##### 2.2 信号描述 - **时钟信号**: 提供系统所需的时钟频率。 - **复位信号**: 用于复位系统，确保正常启动。 - **电源信号**: 包括核心电压、I/O电压等。 - **数据信号**: 包括数据总线和特定外设的数据传输信号。 - **地址信号**: 地址总线信号，用于寻址。 #### 三、功能概述 ##### 3.1 内存映射 - **内存结构**: 包括程序存储空间、数据存储空间及特殊功能寄存器空间等。 - **寻址范围**: 描述了各部分内存的起始地址及大小。 - **访问方式**: 介绍了如何通过指令集访问这些内存区域。 ##### 3.2 简要描述 - **C28x CPU**: 提供了详细的C28x CPU架构和指令集信息。 - **哈佛总线架构**: 解释了数据总线和指令总线分离的设计理念及其优点。 - **外围总线**: 介绍了连接CPU和其他外设的总线结构。 - **实时JTAG和分析**: 描述了调试接口的功能和使用方法。 - **外部接口 (XINTF)**: 说明了扩展外设的能力。 - **闪存**: 介绍了片内闪存的特性和使用注意事项。 - **M0, M1 SRAMs**: 讲解了两种类型的静态随机存取存储器的特点。 - **L0-L7 SRAMs**: 详细说明了这几种类型的SRAM在系统中的作用。 - **Boot ROM**: 解析了启动ROM的作用，包括启动代码和引导加载程序。 - **安全特性**: 介绍了安全相关的配置选项和技术细节。 - **PIE块**: 描述了外围中断扩展块的工作原理和配置方法。 - **外部中断**: 说明了外部中断输入的使用场景和配置步骤。 - **振荡器和PLL**: 介绍了系统时钟源的选择和配置方法。 - **看门狗**: 说明了看门狗定时器的功能和使用方法。 - **外围时钟**: 介绍了不同外设的时钟分配机制。 - **低功耗模式**: 解释了各种低功耗模式的实现原理和配置方法。 - **外围帧 (PFn)**: 介绍了如何配置和管理不同的外围模块。 - **GPIO复用器**: 解释了如何通过GPIO复用器来配置引脚功能。 - **32位CPU定时器**: 介绍了三个32位CPU定时器的功能和使用方法。 - **控制外设**: 详细描述了包括ADC、PWM等在内的控制外设模块。 ##### 3.3 寄存器映射 - **寄存器结构**: 列出了各个功能模块的关键寄存器。 - **配置方法**: 说明了如何通过写入特定值来配置这些寄存器。 ##### 3.4 设备仿真寄存器 - **仿真支持**: 介绍了支持仿真调试的相关寄存器。 ##### 3.5 中断 - **中断类型**: 包括内部中断和外部中断的详细介绍。 - **中断处理**: 解释了中断响应机制和中断服务程序的编写方法。 ##### 3.6 系统控制 - **时钟与PLL模块**: 详细介绍了时钟源的选择和PLL的配置方法。 - **看门狗块**: 介绍了看门狗定时器的配置和使用方法。 - **低功耗模式块**: 说明了如何配置系统进入低功耗模式。 #### 四、外设介绍 ##### 4.1 DMA总览 - **DMA结构**: 介绍了DMA控制器的架构特点。 - **DMA操作**: 说明了DMA传输的基本流程和控制方法。 ##### 4.2 32位CPU定时器 - **定时器功能**: 介绍了三个32位CPU定时器的具体功能。 - **配置与使用**: 说明了如何配置这些定时器以满足不同的计时需求。 ##### 4.3 增强型PWM模块 - **PWM特性**: 介绍了增强型PWM模块的主要特性。 - **配置方法**: 说明了如何配置PWM参数以实现精确的脉冲宽度调制。 ##### 4.4 高分辨率PWM (HRPWM) - **HRPWM特性**: 介绍了高分辨率PWM模块的特点和优势。 - **配置与使用**: 说明了如何利用HRPWM来提高PWM信号的精度。 ##### 4.5 增强型捕获模块 - **捕获功能**: 介绍了增强型捕获模块的主要功能。 - **配置方法**: 说明了如何配置捕获参数以实现精确的时间测量。 ##### 4.6 增强型QEP模块 - **QEP功能**: 介绍了增强型四相编码器模块的主要功能。 - **配置与使用**: 说明了如何配置QEP参数以实现精确的位置检测。 ##### 4.7 模拟到数字转换器 (ADC) 模块 - **ADC特性**: 介绍了ADC模块的主要特性。 - **配置方法**: 说明了如何配置ADC参数以实现精确的模拟信号转换。 TMS320F2833x 和 TMS320F2823x 系列DSCs提供了丰富的硬件资源和功能模块，适用于多种复杂的应用场景。开发者可以根据实际需求选择合适的资源进行开发，并利用详尽的技术文档来深入了解每个模块的特性和使用方法。
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TMS320F28335, TMS320F28334, TMS320F28332
TMS320F28235, TMS320F28234, TMS320F28232
Digital Signal Controllers (DSCs)
Data Manual
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Literature Number: SPRS439M
June 2007–Revised August 2012
TMS320F28335, TMS320F28334, TMS320F28332
TMS320F28235, TMS320F28234, TMS320F28232
www.ti.com
SPRS439M –JUNE 2007–REVISED AUGUST 2012
Contents
1 TMS320F2833x, TMS320F2823x DSCs .................................................................................. 10
1.1 Features .................................................................................................................... 10
1.2 Getting Started ............................................................................................................. 11
2 Introduction ...................................................................................................................... 12
2.1 Pin Assignments ........................................................................................................... 14
2.2 Signal Descriptions ........................................................................................................ 23
3 Functional Overview .......................................................................................................... 33
3.1 Memory Maps .............................................................................................................. 34
3.2 Brief Descriptions .......................................................................................................... 41
3.2.1 C28x CPU ....................................................................................................... 41
3.2.2 Memory Bus (Harvard Bus Architecture) .................................................................... 41
3.2.3 Peripheral Bus .................................................................................................. 41
3.2.4 Real-Time JTAG and Analysis ................................................................................ 42
3.2.5 External Interface (XINTF) .................................................................................... 42
3.2.6 Flash ............................................................................................................. 42
3.2.7 M0, M1 SARAMs ............................................................................................... 42
3.2.8 L0, L1, L2, L3, L4, L5, L6, L7 SARAMs ..................................................................... 43
3.2.9 Boot ROM ........................................................................................................ 43
3.2.9.1 Peripheral Pins Used by the Bootloader ........................................................ 44
3.2.10 Security .......................................................................................................... 44
3.2.11 Peripheral Interrupt Expansion (PIE) Block ................................................................. 46
3.2.12 External Interrupts (XINT1–XINT7, XNMI) .................................................................. 46
3.2.13 Oscillator and PLL .............................................................................................. 46
3.2.14 Watchdog ........................................................................................................ 46
3.2.15 Peripheral Clocking ............................................................................................. 46
3.2.16 Low-Power Modes .............................................................................................. 46
3.2.17 Peripheral Frames 0, 1, 2, 3 (PFn) ........................................................................... 47
3.2.18 General-Purpose Input/Output (GPIO) Multiplexer ......................................................... 47
3.2.19 32-Bit CPU-Timers (0, 1, 2) ................................................................................... 47
3.2.20 Control Peripherals ............................................................................................. 48
3.2.21 Serial Port Peripherals ......................................................................................... 48
3.3 Register Map ............................................................................................................... 49
3.4 Device Emulation Registers .............................................................................................. 51
3.5 Interrupts .................................................................................................................... 52
3.5.1 External Interrupts .............................................................................................. 56
3.6 System Control ............................................................................................................ 57
3.6.1 OSC and PLL Block ............................................................................................ 58
3.6.1.1 External Reference Oscillator Clock Option .................................................... 59
3.6.1.2 PLL-Based Clock Module ......................................................................... 60
3.6.1.3 Loss of Input Clock ................................................................................ 61
3.6.2 Watchdog Block ................................................................................................. 62
3.7 Low-Power Modes Block ................................................................................................. 63
4 Peripherals ....................................................................................................................... 64
4.1 DMA Overview ............................................................................................................. 64
4.2 32-Bit CPU-Timer 0, CPU-Timer 1, CPU-Timer 2 ..................................................................... 66
4.3 Enhanced PWM Modules ................................................................................................ 68
4.4 High-Resolution PWM (HRPWM) ....................................................................................... 72
4.5 Enhanced CAP Modules ................................................................................................. 73
4.6 Enhanced QEP Modules ................................................................................................. 75
4.7 Analog-to-Digital Converter (ADC) Module ............................................................................ 77
4.7.1 ADC Connections if the ADC Is Not Used .................................................................. 81
2 Contents Copyright © 2007–2012, Texas Instruments Incorporated
TMS320F28335, TMS320F28334, TMS320F28332
TMS320F28235, TMS320F28234, TMS320F28232
www.ti.com
SPRS439M –JUNE 2007–REVISED AUGUST 2012
4.7.2 ADC Registers .................................................................................................. 82
4.7.3 ADC Calibration ................................................................................................. 83
4.8 Multichannel Buffered Serial Port (McBSP) Module .................................................................. 83
4.9 Enhanced Controller Area Network (eCAN) Modules (eCAN-A and eCAN-B) .................................... 86
4.10 Serial Communications Interface (SCI) Modules (SCI-A, SCI-B, SCI-C) .......................................... 91
4.11 Serial Peripheral Interface (SPI) Module (SPI-A) ..................................................................... 95
4.12 Inter-Integrated Circuit (I2C) ............................................................................................. 98
4.13 GPIO MUX ................................................................................................................. 99
4.14 External Interface (XINTF) .............................................................................................. 106
5 Device Support ................................................................................................................ 108
5.1 Device and Development Support Tool Nomenclature ............................................................. 108
5.2 Documentation Support ................................................................................................. 110
5.3 Community Resources .................................................................................................. 115
6 Electrical Specifications ................................................................................................... 116
6.1 Absolute Maximum Ratings ............................................................................................ 116
6.2 Recommended Operating Conditions ................................................................................. 117
6.3 Electrical Characteristics ................................................................................................ 117
6.4 Current Consumption .................................................................................................... 118
6.4.1 Reducing Current Consumption ............................................................................. 120
6.4.2 Current Consumption Graphs ............................................................................... 121
6.4.3 Thermal Design Considerations ............................................................................. 122
6.5 Emulator Connection Without Signal Buffering for the DSP ....................................................... 123
6.6 Timing Parameter Symbology .......................................................................................... 124
6.6.1 General Notes on Timing Parameters ...................................................................... 124
6.6.2 Test Load Circuit .............................................................................................. 124
6.6.3 Device Clock Table ........................................................................................... 125
6.7 Clock Requirements and Characteristics ............................................................................. 126
6.8 Power Sequencing ....................................................................................................... 127
6.8.1 Power Management and Supervisory Circuit Solutions .................................................. 128
6.9 General-Purpose Input/Output (GPIO) ................................................................................ 131
6.9.1 GPIO - Output Timing ........................................................................................ 131
6.9.2 GPIO - Input Timing .......................................................................................... 132
6.9.3 Sampling Window Width for Input Signals ................................................................. 133
6.9.4 Low-Power Mode Wakeup Timing .......................................................................... 134
6.10 Enhanced Control Peripherals ......................................................................................... 139
6.10.1 Enhanced Pulse Width Modulator (ePWM) Timing ....................................................... 139
6.10.2 Trip-Zone Input Timing ....................................................................................... 139
6.10.3 High-Resolution PWM Timing ............................................................................... 140
6.10.4 Enhanced Capture (eCAP) Timing ......................................................................... 140
6.10.5 Enhanced Quadrature Encoder Pulse (eQEP) Timing ................................................... 141
6.10.6 ADC Start-of-Conversion Timing ............................................................................ 142
6.11 External Interrupt Timing ................................................................................................ 142
6.12 I2C Electrical Specification and Timing ............................................................................... 143
6.13 Serial Peripheral Interface (SPI) Timing .............................................................................. 143
6.13.1 Master Mode Timing .......................................................................................... 143
6.13.2 SPI Slave Mode Timing ...................................................................................... 148
6.14 External Interface (XINTF) Timing ..................................................................................... 151
6.14.1 USEREADY = 0 ............................................................................................... 151
6.14.2 Synchronous Mode (USEREADY = 1, READYMODE = 0) ............................................. 152
6.14.3 Asynchronous Mode (USEREADY = 1, READYMODE = 1) ............................................ 153
6.14.4 XINTF Signal Alignment to XCLKOUT ..................................................................... 155
6.14.5 External Interface Read Timing ............................................................................. 156
6.14.6 External Interface Write Timing ............................................................................. 158
Copyright © 2007–2012, Texas Instruments Incorporated Contents 3
TMS320F28335, TMS320F28334, TMS320F28332
TMS320F28235, TMS320F28234, TMS320F28232
SPRS439M –JUNE 2007–REVISED AUGUST 2012
www.ti.com
6.14.7 External Interface Ready-on-Read Timing With One External Wait State ............................ 160
6.14.8 External Interface Ready-on-Write Timing With One External Wait State ............................. 163
6.14.9 XHOLD and XHOLDA Timing ............................................................................... 166
6.15 On-Chip Analog-to-Digital Converter .................................................................................. 169
6.15.1 ADC Power-Up Control Bit Timing .......................................................................... 170
6.15.2 Definitions ...................................................................................................... 171
6.15.3 Sequential Sampling Mode (Single-Channel) (SMODE = 0) ............................................ 172
6.15.4 Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1) .......................................... 173
6.15.5 Detailed Descriptions ......................................................................................... 174
6.16 Multichannel Buffered Serial Port (McBSP) Timing ................................................................. 175
6.16.1 McBSP Transmit and Receive Timing ...................................................................... 175
6.16.2 McBSP as SPI Master or Slave Timing .................................................................... 178
6.17 Flash Timing .............................................................................................................. 182
6.18 Migrating Between F2833x Devices and F2823x Devices ......................................................... 184
7 L-to-M Revision History .................................................................................................... 185
8 K-to-L Revision History .................................................................................................... 186
9 Thermal and Mechanical Data ............................................................................................ 187
4 Contents Copyright © 2007–2012, Texas Instruments Incorporated
TMS320F28335, TMS320F28334, TMS320F28332
TMS320F28235, TMS320F28234, TMS320F28232
www.ti.com
SPRS439M –JUNE 2007–REVISED AUGUST 2012
List of Figures
2-1 F2833x, F2823x 176-Pin PGF/PTP LQFP (Top View) ...................................................................... 14
2-2 F2833x, F2823x 179-Ball ZHH MicroStar BGA™ (Upper Left Quadrant) (Bottom View) .............................. 16
2-3 F2833x, F2823x 179-Ball ZHH MicroStar BGA™ (Upper Right Quadrant) (Bottom View)............................. 17
2-4 F2833x, F2823x 179-Ball ZHH MicroStar BGA™ (Lower Left Quadrant) (Bottom View) .............................. 18
2-5 F2833x, F2823x 179-Ball ZHH MicroStar BGA ™(Lower Right Quadrant) (Bottom View)............................. 19
2-6 F2833x, F2823x 176-Ball ZJZ Plastic BGA (Upper Left Quadrant) (Bottom View)...................................... 20
2-7 F2833x, F2823x 176-Ball ZJZ Plastic BGA (Upper Right Quadrant) (Bottom View).................................... 21
2-8 F2833x, F2823x 176-Ball ZJZ Plastic BGA (Lower Left Quadrant) (Bottom View)...................................... 22
2-9 F2833x, F2823x 176-Ball ZJZ Plastic BGA (Lower Right Quadrant) (Bottom View).................................... 22
3-1 Functional Block Diagram ...................................................................................................... 34
3-2 F28335, F28235 Memory Map ................................................................................................. 36
3-3 F28334, F28234 Memory Map ................................................................................................. 37
3-4 F28332, F28232 Memory Map ................................................................................................. 37
3-5 External and PIE Interrupt Sources............................................................................................ 53
3-6 External Interrupts................................................................................................................ 53
3-7 Multiplexing of Interrupts Using the PIE Block ............................................................................... 54
3-8 Clock and Reset Domains ...................................................................................................... 57
3-9 OSC and PLL Block Diagram................................................................................................... 58
3-10 Using a 3.3-V External Oscillator............................................................................................... 59
3-11 Using a 1.9-V External Oscillator............................................................................................... 59
3-12 Using the Internal Oscillator .................................................................................................... 59
3-13 Watchdog Module ................................................................................................................ 62
4-1 DMA Functional Block Diagram ................................................................................................ 65
4-2 CPU-Timers....................................................................................................................... 66
4-3 CPU-Timer Interrupt Signals and Output Signal ............................................................................. 66
4-4 Time-Base Counter Synchronization Scheme 3 ............................................................................. 68
4-5 ePWM Submodules Showing Critical Internal Signal Interconnections ................................................... 71
4-6 eCAP Functional Block Diagram ............................................................................................... 73
4-7 eQEP Functional Block Diagram............................................................................................... 75
4-8 Block Diagram of the ADC Module ............................................................................................ 78
4-9 ADC Pin Connections With Internal Reference .............................................................................. 79
4-10 ADC Pin Connections With External Reference ............................................................................. 80
4-11 McBSP Module .................................................................................................................. 84
4-12 eCAN Block Diagram and Interface Circuit ................................................................................... 87
4-13 eCAN-A Memory Map ........................................................................................................... 88
4-14 eCAN-B Memory Map ........................................................................................................... 89
4-15 Serial Communications Interface (SCI) Module Block Diagram............................................................ 94
4-16 SPI Module Block Diagram (Slave Mode) .................................................................................... 97
4-17 I2C Peripheral Module Interfaces .............................................................................................. 98
4-18 GPIO MUX Block Diagram .................................................................................................... 100
4-19 Qualification Using Sampling Window ....................................................................................... 105
4-20 External Interface Block Diagram............................................................................................. 106
4-21 Typical 16-bit Data Bus XINTF Connections................................................................................ 107
4-22 Typical 32-bit Data Bus XINTF Connections................................................................................ 107
5-1 Example of F2833x, F2823x Device Nomenclature........................................................................ 109
6-1 Typical Operational Current Versus Frequency (F28335, F28235, F28334, F28234)................................. 122
6-2 Typical Operational Power Versus Frequency (F28335, F28235, F28334, F28234) .................................. 122
Copyright © 2007–2012, Texas Instruments Incorporated List of Figures 5
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