ECCN 5E002 TSPA – Technology / Software Publicly Available
MSP430x5xx and MSP430x6xx Family
User's Guide
Literature Number: SLAU208M
June 2008–Revised February 2013
Contents
Preface ...................................................................................................................................... 51
1 System Resets, Interrupts, and Operating Modes, System Control Module (SYS) ...................... 53
1.1 System Control Module (SYS) Introduction ............................................................................ 54
1.2 System Reset and Initialization .......................................................................................... 54
1.2.1 Device Initial Conditions After System Reset ................................................................. 56
1.3 Interrupts .................................................................................................................... 56
1.3.1 (Non)Maskable Interrupts (NMIs) ............................................................................... 57
1.3.2 SNMI Timing ...................................................................................................... 58
1.3.3 Maskable Interrupts .............................................................................................. 59
1.3.4 Interrupt Processing .............................................................................................. 59
1.3.5 Interrupt Nesting .................................................................................................. 60
1.3.6 Interrupt Vectors .................................................................................................. 60
1.3.7 SYS Interrupt Vector Generators ............................................................................... 61
1.4 Operating Modes .......................................................................................................... 62
1.4.1 Entering and Exiting Low-Power Modes LPM0 Through LPM4 ............................................ 65
1.4.2 Entering and Exiting Low-Power Modes LPMx.5 ............................................................. 65
1.4.3 Extended Time in Low-Power Modes .......................................................................... 66
1.5 Principles for Low-Power Applications .................................................................................. 68
1.6 Connection of Unused Pins .............................................................................................. 68
1.7 Reset Pin (RST/NMI) Configuration ..................................................................................... 69
1.8 Configuring JTAG pins .................................................................................................... 69
1.9 Boot Code .................................................................................................................. 69
1.10 Bootstrap Loader (BSL) .................................................................................................. 69
1.11 Memory Map – Uses and Abilities ...................................................................................... 71
1.11.1 Vacant Memory Space ......................................................................................... 71
1.11.2 JTAG Lock Mechanism via the Electronic Fuse ............................................................. 71
1.12 JTAG Mailbox (JMB) System ............................................................................................ 72
1.12.1 JMB Configuration ............................................................................................... 72
1.12.2 JMBOUT0 and JMBOUT1 Outgoing Mailbox ................................................................ 72
1.12.3 JMBIN0 and JMBIN1 Incoming Mailbox ...................................................................... 72
1.12.4 JMB NMI Usage ................................................................................................. 73
1.13 Device Descriptor Table .................................................................................................. 73
1.13.1 Identifying Device Type ......................................................................................... 74
1.13.2 TLV Descriptors ................................................................................................. 75
1.13.3 Peripheral Discovery Descriptor ............................................................................... 76
1.13.4 CRC Computation ............................................................................................... 80
1.13.5 Calibration Values ............................................................................................... 81
1.14 SFR Registers ............................................................................................................. 83
1.14.1 SFRIE1 Register ................................................................................................. 84
1.14.2 SFRIFG1 Register ............................................................................................... 85
1.14.3 SFRRPCR Register ............................................................................................. 87
1.15 SYS Registers ............................................................................................................. 88
1.15.1 SYSCTL Register ................................................................................................ 89
1.15.2 SYSBSLC Register .............................................................................................. 90
1.15.3 SYSJMBC Register ............................................................................................. 91
3
SLAU208M–June 2008–Revised February 2013 Contents
Submit Documentation Feedback
Copyright © 2008–2013, Texas Instruments Incorporated
ECCN 5E002 TSPA – Technology / Software Publicly Available
www.ti.com
1.15.4 SYSJMBI0 Register ............................................................................................. 92
1.15.5 SYSJMBI1 Register ............................................................................................. 92
1.15.6 SYSJMBO0 Register ............................................................................................ 93
1.15.7 SYSJMBO1 Register ............................................................................................ 93
1.15.8 SYSUNIV Register .............................................................................................. 94
1.15.9 SYSSNIV Register .............................................................................................. 95
1.15.10 SYSRSTIV Register ........................................................................................... 96
1.15.11 SYSBERRIV Register ......................................................................................... 97
2 Power Management Module and Supply Voltage Supervisor ................................................... 98
2.1 Power Management Module (PMM) Introduction ..................................................................... 99
2.2 PMM Operation ........................................................................................................... 101
2.2.1 V
CORE
and the Regulator ........................................................................................ 101
2.2.2 Supply Voltage Supervisor and Monitor ..................................................................... 101
2.2.3 Supply Voltage Supervisor and Monitor - Power-Up ....................................................... 107
2.2.4 Increasing V
CORE
to Support Higher MCLK Frequencies ................................................... 107
2.2.5 Decreasing V
CORE
for Power Optimization .................................................................... 109
2.2.6 Transition From LPM3 and LPM4 Modes to AM ............................................................ 109
2.2.7 LPM3.5 and LPM4.5 ............................................................................................ 109
2.2.8 Brownout Reset (BOR), Software BOR, Software POR ................................................... 109
2.2.9 SVS and SVM Performance Modes and Wakeup Times .................................................. 110
2.2.10 PMM Interrupts ................................................................................................. 113
2.2.11 Port I/O Control ................................................................................................. 113
2.2.12 Supply Voltage Monitor Output (SVMOUT, Optional) ..................................................... 113
2.3 PMM Registers ........................................................................................................... 114
2.3.1 PMMCTL0 Register ............................................................................................. 115
2.3.2 PMMCTL1 Register ............................................................................................. 116
2.3.3 SVSMHCTL Register ........................................................................................... 117
2.3.4 SVSMLCTL Register ........................................................................................... 118
2.3.5 SVSMIO Register ............................................................................................... 119
2.3.6 PMMIFG Register ............................................................................................... 120
2.3.7 PMMRIE Register ............................................................................................... 122
2.3.8 PM5CTL0 Register ............................................................................................. 123
3 Battery Backup System .................................................................................................... 124
3.1 Battery Backup Introduction ............................................................................................ 125
3.2 Battery Backup Operation .............................................................................................. 125
3.2.1 Battery Backup Switch Control ................................................................................ 126
3.2.2 LPMx.5 and Backup Operation ................................................................................ 127
3.2.3 Resistive Charger ............................................................................................... 127
3.3 Battery Backup Registers ............................................................................................... 128
3.3.1 BAKCTL Register ............................................................................................... 129
3.3.2 BAKCHCTL Register ........................................................................................... 130
4 Auxiliary Supply System (AUX) .......................................................................................... 131
4.1 Auxiliary Supply System Introduction ................................................................................. 132
4.2 Auxiliary Supply Operation .............................................................................................. 133
4.2.1 Startup ............................................................................................................ 134
4.2.2 Switching Control ............................................................................................... 134
4.2.3 Software-Controlled Switching ................................................................................ 134
4.2.4 Hardware-Controlled Switching ............................................................................... 135
4.2.5 Interactions Among f
SYS
, V
CORE
, V
DSYS
, SVM
H
, and AUXxLVL .............................................. 136
4.2.6 Auxiliary Supply Monitor ....................................................................................... 138
4.2.7 LPMx.5 and Auxiliary Supply Operation ..................................................................... 139
4.2.8 Digital I/Os and Auxiliary Supplies ............................................................................ 140
4.2.9 Measuring the Supplies ........................................................................................ 141
4
Contents SLAU208M–June 2008–Revised February 2013
Submit Documentation Feedback
Copyright © 2008–2013, Texas Instruments Incorporated
ECCN 5E002 TSPA – Technology / Software Publicly Available
www.ti.com
4.2.10 Resistive Charger .............................................................................................. 142
4.2.11 Auxiliary Supply Interrupts .................................................................................... 142
4.2.12 Software Flow .................................................................................................. 143
4.2.13 Examples of AUX Operation ................................................................................. 145
4.3 AUX Registers ............................................................................................................ 147
4.3.1 AUXCTL0 Register ............................................................................................. 148
4.3.2 AUXCTL1 Register ............................................................................................. 149
4.3.3 AUXCTL2 Register ............................................................................................. 150
4.3.4 AUX2CHCTL Register .......................................................................................... 151
4.3.5 AUX3CHCTL Register .......................................................................................... 152
4.3.6 AUXADCCTL Register ......................................................................................... 153
4.3.7 AUXIFG Register ................................................................................................ 154
4.3.8 AUXIE Register .................................................................................................. 155
4.3.9 AUXIV Register .................................................................................................. 156
5 Unified Clock System (UCS) .............................................................................................. 157
5.1 Unified Clock System (UCS) Introduction ............................................................................ 158
5.2 UCS Operation ........................................................................................................... 160
5.2.1 UCS Module Features for Low-Power Applications ........................................................ 160
5.2.2 Internal Very-Low-Power Low-Frequency Oscillator (VLO) ............................................... 160
5.2.3 Internal Trimmed Low-Frequency Reference Oscillator (REFO) ......................................... 161
5.2.4 XT1 Oscillator ................................................................................................... 161
5.2.5 XT2 Oscillator ................................................................................................... 162
5.2.6 Digitally-Controlled Oscillator (DCO) ......................................................................... 163
5.2.7 Frequency Locked Loop (FLL) ................................................................................ 164
5.2.8 DCO Modulator .................................................................................................. 164
5.2.9 Disabling FLL Hardware and Modulator ..................................................................... 165
5.2.10 FLL Operation From Low-Power Modes .................................................................... 165
5.2.11 Operation From Low-Power Modes, Requested by Peripheral Modules ............................... 165
5.2.12 UCS Module Fail-Safe Operation ............................................................................ 167
5.2.13 Synchronization of Clock Signals ............................................................................ 170
5.3 Module Oscillator (MODOSC) .......................................................................................... 171
5.3.1 MODOSC Operation ............................................................................................ 171
5.4 UCS Module Registers .................................................................................................. 172
5.4.1 UCSCTL0 Register ............................................................................................. 173
5.4.2 UCSCTL1 Register ............................................................................................. 174
5.4.3 UCSCTL2 Register ............................................................................................. 175
5.4.4 UCSCTL3 Register ............................................................................................. 176
5.4.5 UCSCTL4 Register ............................................................................................. 177
5.4.6 UCSCTL5 Register ............................................................................................. 178
5.4.7 UCSCTL6 Register ............................................................................................. 180
5.4.8 UCSCTL7 Register ............................................................................................. 182
5.4.9 UCSCTL8 Register ............................................................................................. 183
5.4.10 UCSCTL9 Register ............................................................................................ 184
6 CPUX .............................................................................................................................. 185
6.1 MSP430X CPU (CPUX) Introduction .................................................................................. 186
6.2 Interrupts .................................................................................................................. 188
6.3 CPU Registers ............................................................................................................ 189
6.3.1 Program Counter (PC) ......................................................................................... 189
6.3.2 Stack Pointer (SP) .............................................................................................. 189
6.3.3 Status Register (SR) ............................................................................................ 191
6.3.4 Constant Generator Registers (CG1 and CG2) ............................................................. 192
6.3.5 General-Purpose Registers (R4 –R15) ...................................................................... 193
6.4 Addressing Modes ....................................................................................................... 195
5
SLAU208M–June 2008–Revised February 2013 Contents
Submit Documentation Feedback
Copyright © 2008–2013, Texas Instruments Incorporated
- 1
- 2
前往页