MC74HC153D_datasheet.zip

SEMICONDUCTOR TECHNICAL DATA

REV 6

 Motorola, Inc. 1995

10/95

• Output Drive Capability: 10 LSTTL Loads

• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 2 to 6 V

• Low Input Current: 1 µA

• High Noise Immunity Characteristic of CMOS Devices

• In Compliance with the Requirements Defined by JEDEC Standard

• Chip Complexity: 108 FETs or 27 Equivalent Gates

a

PIN 16 = V

CC

PIN 8 = GND

2

b

DATA–

WORD b

INPUTS

b

b

X X H L

L L L D0

L H L D1

H L L D2

H H L D3

13

14

4

3

2

1

8

7

6

STROBE a

D3

a

A1

D2

a

D1

a

D0

a

Y

a

CASE 751B–05

PLASTIC PACKAGE

CASE 648–08

85

Minimum High–Level Input

V

out

= 0.1 V or V

CC

– 0.1 V

1.5

1.5

Maximum Low–Level Input

Voltage

V

out

= 0.1 V or V

CC

– 0.1 V

|I

out

|

20 µA

0.3

0.9

1.2

0.3

0.9

1.2

V

in

IH

|I

out

|

20 µA

1.9

4.4

5.9

1.9

4.4

5.9

V

in

IH

0.26

0.26

0.33

0.33

0.40

0.40

I

CC

Maximum Quiescent Supply

Current (per Package)

V

in

CC

I

NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

This device contains protection

circuitry to guard against damage

due to high static voltages or electric

V

out

range GND

in

Unused inputs must always be

tied to an appropriate logic voltage

level (e.g., either GND or V

Unused outputs must be left open.