Command Line Tools User Guide（命令行工具用户指南）

CommandLineToolsUser

Guide

(FormerlytheDevelopmentSystemReferenceGuide)

UG628(v12.2)July23,2010

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CommandLineToolsUserGuide

-f(ExecuteCommandsFile)..............................................................................18

-h(Help).........................................................................................................19

-intstyle(IntegrationStyle)...............................................................................20

-p(PartNumber).............................................................................................21

InvokingCommandLinePrograms....................................................................22

Chapter2DesignFlow...............................................................................................23

DesignFlowOverview........................................................................................23

DesignEntryandSynthesis................................................................................26

HierarchicalDesign.............................................................................................26

Partitions...............................................................................................................27

Constraints...........................................................................................................29

MappingConstraints(FPGAsOnly)..................................................................29

BlockPlacement...............................................................................................30

TimingSpecications.......................................................................................30

NetlistTranslationPrograms...............................................................................30

DesignImplementation.......................................................................................30

Mapping(FPGAsOnly).......................................................................................32

PlacingandRouting(FPGAsOnly)....................................................................33

BitstreamGeneration(FPGAsOnly)..................................................................33

DesignVerication...............................................................................................33

StaticTimingAnalysis(FPGAsOnly)................................................................39

In-CircuitVerication..........................................................................................39

DesignRuleChecker(FPGAsOnly)..................................................................39

Probe..............................................................................................................39

CommandLineToolsUserGuide

UG628(v12.2)July23,2010www.xilinx.com3

ChipScope™ILAandChipScopePro................................................................39

FPGADesignTips...............................................................................................39

DesignSizeandPerformance............................................................................40

Chapter3PARTGen...................................................................................................41

PARTGenSyntax..................................................................................................47

PARTGenCommandLineOptions.....................................................................47

-arch(OutputInformationforSpeciedArchitecture)........................................48

-i(OutputListofDevices,Packages,andSpeeds)...............................................48

-intstyle(IntegrationStyle)...............................................................................48

-nopkgle(GenerateNoPackageFile)...............................................................49

-p(GeneratePartlistandPackageFiles).............................................................49

-v(GeneratePartlistandPackageFiles).............................................................50

Chapter4NetGen.......................................................................................................51

NetGenOverview................................................................................................51

Verilog-SpecicOptionsforFunctionalandTimingSimulation..........................60

VHDL-SpecicOptionsforFunctionalandTimingSimulation...........................62

NetGenEquivalenceCheckingFlow..................................................................63

Post-NGDBuildFlowforFPGAs.......................................................................63

Post-ImplementationFlowforFPGAs...............................................................63

InputlesforNetGenEquivalenceChecking.....................................................64

OutputlesforNetGenEquivalenceChecking..................................................64

SyntaxforNetGenEquivalenceChecking..........................................................64

OptionsforNetGenEquivalenceCheckingFlow................................................65

NetGenStaticTimingAnalysisFlow.................................................................67

TestbenchFile..................................................................................................72

HierarchyInformationFile...............................................................................72

DedicatedGlobalSignalsinBack-AnnotationSimulation..............................73

GlobalSignalsinVerilogNetlist........................................................................73

GlobalSignalsinVHDLNetlist.........................................................................73

CommandLineToolsUserGuide

4www.xilinx.comUG628(v12.2)July23,2010

Chapter5LogicalDesignRuleCheck(DRC)...........................................................75

LogicalDRCOverview........................................................................................75

LogicalDRCDeviceSupport............................................................................75

LogicalDRCChecks............................................................................................76

BlockCheck.....................................................................................................76

NetCheck.......................................................................................................76