http://www.doc88.com/p-417988938409.html
entity f100 is
port(clk:in std_logic:='1';
sec:out std_logic);
end entity f100;
architecture getsec of f100 is
signal secout :std_logic:='1';
begin
process(clk) is
variable count100:integer range 0 to 50;
begin
if clk'event and clk='1' then
count100:=count100+1;
if count100=50 then
secout<=not secout;
count100:=0;
end if;
end if;
end process;
sec<=secout;
end architecture getsec;
entity f10 is
port(clk:in sta_logic ;
sec:out std_logic);
end entity f10;
architecture getsec of f10 is
signal secout:std_logic:='1';
begin
process(clk)is
variable count10:integer range 0 to 5;
begin
if clk'event and clk='1' then
count10:=count10+1;
if count10=5 then
secout<= not secout;
count10:=0;
end if;
end if;
end process;
sec<=secout;
end architecture getsec;
ËٶȿØÖÆ
entity speed is
port(clk,clr:in std_logic;
data;in std_logic_vector (1 downto 0)£»
spd_out:out std_logic);
architecture arch of speed is
