library ieee;
use ieee.std_logic_1164.all;
entity dian2_zhang is
port(clk,d:in std_logic;
y:out std_logic);
end dian2_zhang;
architecture guochao of dian2_zhang is
type state is (s0,s1,s2,s3,s4);
signal current_state,next_state:state;
begin
process(clk)
begin
if rising_edge(clk) then
current_state<=next_state;
end if;
end process;
process(d,current_state,next_state)
begin
case current_state is
when s0=> y<='0';
if d='1' then next_state<=s1;
else next_state<=s0;
end if;
when s1=> y<='0';
if d='0' then next_state<=s2;
else next_state<=s0;
end if;
when s2=> y<='0';
if d='1' then next_state<=s3;
else next_state<=s0;
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