模拟数字转换ADC0804资源-CSDN文库

需积分: 9 27 浏览量 2013-08-05 21:12:18 上传评论 1 收藏 1.09MB PDF 举报

模拟数字转换器（ADC）是一种电子设备，它能将连续的模拟信号转换成离散的数字信号。ADC0804是模拟数字转换器的一种，属于8位微处理器兼容的逐次逼近型A/D转换器系列，由国家半导体公司设计制造。ADC0804可以将模拟信号按照特定的分辨率转换为数字信号，广泛应用于需要模拟信号数字化的各种电子系统中。 ADC0804的特点包括与8080微处理器兼容，无需额外的接口逻辑即可直接与微处理器连接。它支持CMOS工艺，能够接受0V到5V的模拟输入电压范围，并且在单5V供电的情况下工作。这些A/D转换器内置了三态输出锁存器，可以直接驱动数据总线，因此它们对微处理器来说就像是内存位置或者I/O端口一样。 ADC0804使用了逐次逼近的转换方法，这种技术涉及对输入电压的逐次逼近，直到得到与之对应的数字值。它还提供差分模拟电压输入，这有助于提高共模抑制比，并且可以调整模拟零输入电压值，从而改善转换精度。此外，参考电压输入也可以调整，使得较小的模拟电压范围可以编码为完整的8位分辨率。 ADC0804的主要技术指标如下： 1. 分辨率：8位 2. 转换时间：100微秒 3. 总误差：±1/4 LSB（最小），±1 LSB（最大） 4. 逻辑输入和输出兼容MOS和TTL电平规格 5. 内部集成振荡器，简化了时钟信号的生成 6. 电源电压：5V单电源供电 7. 封装形式：0.3英寸宽度的20脚双列直插封装（DIP），或20脚小外形封装（SO） 8. 工作温度范围：0°C至+70°C或-40°C至+85°C，具体取决于型号除了ADC0804外，文档还提到了同一系列的其他几款产品，包括ADC0801、ADC0802、ADC0803和ADC0805。这些型号在某些特性或参数上可能存在细微差别，但它们都属于同一技术平台的产品。在应用方面，ADC0804适合于各种需要将模拟信号转换为数字信号的场合，如数据采集系统、音频信号处理、医疗设备、测量仪器和工业控制系统等。由于其简单的接口要求和较高的性能，ADC0804在8位微控制器应用领域中广泛受到欢迎。最后需要注意的是，本文内容中的信息部分来源于1999年11月国家半导体公司的文档资料，有关ADC0804的性能参数和功能特性可能会随着技术进步而有所更新。用户在设计应用时应参照最新的技术数据手册以获得最准确的信息。

资源推荐

资源详情

资源评论

ADC0801/ADC0802/ADC0803/ADC0804/ADC0805

8-Bit µP Compatible A/D Converters

General Description

The ADC0801, ADC0802, ADC0803, ADC0804 and

ADC0805 are CMOS 8-bit successive approximation A/D

converters that use a differential potentiometric

ladder — similar to the 256R products. These converters are

designed to allow operation with the NSC800 and INS8080A

derivative control bus with TRI-STATE

output latches di-

rectly driving the data bus. These A/Ds appear like memory

locations or I/O ports to the microprocessor and no interfac-

ing logic is needed.

Differential analog voltage inputs allow increasing the

common-mode rejection and offsetting the analog zero input

voltage value. In addition, the voltage reference input can be

adjusted to allow encoding any smaller analog voltage span

to the full 8 bits of resolution.

Features

n Compatible with 8080 µP derivatives — no interfacing

logic needed - access time - 135 ns

n Easy interface to all microprocessors, or operates “stand

alone”

n Differential analog voltage inputs

n Logic inputs and outputs meet both MOS and TTL

voltage level specifications

n Works with 2.5V (LM336) voltage reference

n On-chip clock generator

n 0V to 5V analog input voltage range with single 5V

supply

n No zero adjust required

n 0.3" standard width 20-pin DIP package

n 20-pin molded chip carrier or small outline package

n Operates ratiometrically or with 5 V

, 2.5 V

,or

analog span adjusted voltage reference

Key Specifications

n Resolution 8 bits

n Total error

⁄

LSB,

⁄

LSB and

1 LSB

n Conversion time 100 µs

Connection Diagram

Ordering Information

TEMP RANGE 0˚C TO 70˚C 0˚C TO 70˚C −40˚C TO +85˚C

⁄

Bit Adjusted ADC0801LCN

ERROR

⁄

Bit Unadjusted ADC0802LCWM ADC0802LCN

⁄

Bit Adjusted ADC0803LCN

1Bit Unadjusted ADC0804LCWM ADC0804LCN ADC0805LCN/ADC0804LCJ

PACKAGE OUTLINE M20B — Small

Outline

N20A — Molded DIP

TRI-STATE

is a registered trademark of National Semiconductor Corp.

Z-80

is a registered trademark of Zilog Corp.

ADC080X

Dual-In-Line and Small Outline (SO) Packages

DS005671-30

See Ordering Information

November 1999

ADC0801/ADC0802/ADC0803/ADC0804/ADC0805 8-Bit µP Compatible A/D Converters

Absolute Maximum Ratings (Notes 1, 2)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Supply Voltage (V

) (Note 3) 6.5V

Voltage

Logic Control Inputs −0.3V to +18V

At Other Input and Outputs −0.3V to (V

+0.3V)

Lead Temp. (Soldering, 10 seconds)

Dual-In-Line Package (plastic) 260˚C

Dual-In-Line Package (ceramic) 300˚C

Surface Mount Package

Vapor Phase (60 seconds) 215˚C

Infrared (15 seconds) 220˚C

Storage Temperature Range −65˚C to +150˚C

Package Dissipation at T

25˚C 875 mW

ESD Susceptibility (Note 10) 800V

Operating Ratings (Notes 1, 2)

Temperature Range T

MIN

≤T

MAX

ADC0804LCJ −40˚C≤T

≤+85˚C

ADC0801/02/03/05LCN −40˚C≤T

≤+85˚C

ADC0804LCN 0˚C≤T

≤+70˚C

ADC0802/04LCWM 0˚C≤T

≤+70˚C

Range of V

4.5 V

to 6.3 V

Electrical Characteristics

The following specifications apply for V

MIN

≤T

MAX

and f

CLK

640 kHz unless otherwise specified.

Parameter Conditions Min Typ Max Units

ADC0801: Total Adjusted Error (Note 8) With Full-Scale Adj.

⁄

LSB

(See Section 2.5.2)

ADC0802: Total Unadjusted Error (Note 8) V

REF

2.500 V

⁄

LSB

ADC0803: Total Adjusted Error (Note 8) With Full-Scale Adj.

⁄

LSB

(See Section 2.5.2)

ADC0804: Total Unadjusted Error (Note 8) V

REF

2.500 V

1 LSB

ADC0805: Total Unadjusted Error (Note 8) V

REF

/2-No Connection

1 LSB

REF

/2 Input Resistance (Pin 9) ADC0801/02/03/05 2.5 8.0 kΩ

ADC0804 (Note 9) 0.75 1.1 kΩ

Analog Input Voltage Range (Note 4) V(+) or V(−) Gnd–0.05 V

+0.05 V

DC Common-Mode Error Over Analog Input Voltage

1/16

⁄

LSB

Range

Power Supply Sensitivity V

Over

1/16

⁄

LSB

Allowed V

(+) and V

(−)

Voltage Range (Note 4)

AC Electrical Characteristics

The following specifications apply for V

and T

MIN

≤T

MAX

unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Units

Conversion Time f

CLK

640 kHz (Note 6) 103 114 µs

Conversion Time (Notes 5, 6) 66 73 1/f

CLK

Clock Frequency V

5V, (Note 5) 100 640 1460 kHz

Clock Duty Cycle 40 60

CR Conversion Rate in Free-Running INTR tied to WR with

8770 9708 conv/s

Mode CS

CLK

640 kHz

W(WR)L

Width of WR Input (Start Pulse Width) CS

(Note 7) 100 ns

ACC

Access Time (Delay from Falling C

100 pF 135 200 ns

Edge of RD to Output Data Valid)

TRI-STATE Control (Delay C

10 pF, R

10k 125 200 ns

from Rising Edge of RD to

(See TRI-STATE Test

Hi-Z State) Circuits)

Delay from Falling Edge 300 450 ns

of WR or RD to Reset of INTR

Input Capacitance of Logic 5 7.5 pF

Control Inputs

ADC0801/ADC0802/ADC0803/ADC0804/ADC0805

www.national.com3

AC Electrical Characteristics (Continued)

The following specifications apply for V

and T

MIN

≤T

MAX

unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Units

OUT

TRI-STATE Output 5 7.5 pF

Capacitance (Data Buffers)

CONTROL INPUTS [Note: CLK IN (Pin 4) is the input of a Schmitt trigger circuit and is therefore specified separately]

(1) Logical “1” Input Voltage V

5.25 V

2.0 15 V

(Except Pin 4 CLK IN)

(0) Logical “0” Input Voltage V

4.75 V

0.8 V

(Except Pin 4 CLK IN)

(1) Logical “1” Input Current V

0.005 1 µA

(All Inputs)

(0) Logical “0” Input Current V

−1 −0.005 µA

(All Inputs)

CLOCK IN AND CLOCK R

+ CLK IN (Pin 4) Positive Going 2.7 3.1 3.5 V

Threshold Voltage

− CLK IN (Pin 4) Negative 1.5 1.8 2.1 V

Going Threshold Voltage

CLK IN (Pin 4) Hysteresis 0.6 1.3 2.0 V

+)−(V

−)

OUT

(0) Logical “0” CLK R Output I

360 µA 0.4 V

Voltage V

4.75 V

OUT

(1) Logical “1” CLK R Output I

−360 µA 2.4 V

Voltage V

4.75 V

DATA OUTPUTS AND INTR

OUT

(0) Logical “0” Output Voltage

Data Outputs I

OUT

1.6 mA, V

4.75 V

0.4 V

INTR Output I

OUT

1.0 mA, V

4.75 V

0.4 V

OUT

(1) Logical “1” Output Voltage I

−360 µA, V

4.75 V

2.4 V

OUT

(1) Logical “1” Output Voltage I

−10 µA, V

4.75 V

4.5 V

OUT

TRI-STATE Disabled Output V

OUT

−3 µA

Leakage (All Data Buffers) V

OUT

3µA

SOURCE

OUT

Short to Gnd, T

25˚C 4.5 6 mA

SINK

OUT

Short to V

25˚C 9.0 16 mA

POWER SUPPLY

Supply Current (Includes f

CLK

640 kHz,

Ladder Current) V

REF

NC, T

25˚C

and CS

ADC0801/02/03/04LCJ/05 1.1 1.8 mA

ADC0804LCN/LCWM 1.9 2.5 mA

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating

the device beyond its specified operating conditions.

Note 2: All voltages are measured with respect to Gnd, unless otherwise specified. The separate A Gnd point should always be wired to the D Gnd.

Note 3: A zener diode exists, internally, from V

to Gnd and has a typical breakdown voltage of 7 V

Note 4: For V

(−)≥ V

(+) the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input (see block diagram) which will forward conduct

for analog input voltages one diode drop below ground or one diode drop greater than the V

supply. Be careful, during testing at low V

levels (4.5V), as high

level analog inputs (5V) can cause this input diode to conduct–especially at elevated temperatures, and cause errors for analog inputs near full-scale. The spec allows

50 mV forward bias of either diode. This means that as long as the analog V

does not exceed the supply voltage by more than 50 mV, the output code will be correct.

To achieve an absolute 0 V

to5V

input voltage range will therefore require a minimum supply voltage of 4.950 V

over temperature variations, initial tolerance

and loading.

Note 5: Accuracy is guaranteed at f

CLK

640 kHz. At higher clock frequencies accuracy can degrade. For lower clock frequencies, the duty cycle limits can be ex-

tended so long as the minimum clock high time interval or minimum clock low time interval is no less than 275 ns.

Note 6: With an asynchronous start pulse, up to 8 clock periods may be required before the internal clock phases are proper to start the conversion process. The

start request is internally latched, see

Figure 4

and section 2.0.

ADC0801/ADC0802/ADC0803/ADC0804/ADC0805

www.national.com 4