uPD720201/uPD720202 User's Manual: Hardware

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uPD720201/uPD720202 User's Manual: Hardware,瑞萨uPD72021用户手册
NOTES FOR CMOS DEVICES (1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CmOs device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL MAX) and VIH MIN) (2)HANDLING OF UNUSED INPUT PINS: Unconnected CMOs device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc causing malfunction. CMOs devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device 3)PRECAUTION AGAINST ESD: A strong electric field, when exposed to a Mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for Pw boards with mounted semiconductor devices (4)STATUS BEFORE INITIALIZATION: Power-on does not necessarily define the initial status of a mos device Immediately after the power source is turned ON, devices with reset functions have not yet been initialized Hence, power-on does not guarantee output pin levels, I/0 settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions (5 POWER ON/OFF SEQUENCE: In the case of a device that uses different power supplies for the internal operation and extemal interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then le internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device (6)INPUT OF SIGNAL DURING POWER OFF STATE: Do not input signals or an o pull-up power supply while the device is not powered. The current injection that results from input of such a signal or w/o pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device USB logo is a trademark of UsB Implementers Forum, Inc Windows is either a registered trademark or a trademark of Microsoft Corporation in the United states and/or other countries PREFACE Readers This manual is intended for engineers who need to be familiar with the capability of the uPD720201/uPD720202 in order to develop application systems based on it Purpose The purpose of this manual is to help users understand the hardware capabilities (listed below)of the uPD720201/uPD720202 Configuration This manual consists of the following chapters Overview Pin function Register information Power management How to connect to external elements How to access external rom FW download interface Battery charging function Guidance Readers of this manual should already have a general knowledge of electronics logic circuits, and microcomputers Notation This manual uses the following conventions Data bit significance High-order bits on the left side low-order bits on the right side Active low: XXXXB(Pin and signal names are suffixed with B Note Explanation of an indicated part of text Caution: Information requiring the user's special attention Remark Supplementary information Numerical value Binary… xxxx or xxxx Decimal XXX Hexadecimal.. xxxx Related document Use this manual in combination with the following document. The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such uPD720201/u PD720202 Data Sheet: R19DS0047E CONTENTS 1. Overview 1.1 Features 1.2 Applications.……,,…,,…,,,………,…,…,………,…,,……2 1.3 Ordering Information 1.4 Block Diagram… 1.5 Pin Configuration (TOP VIEW) 2. Pin function 2.1 Power supply….......,,…… 22 Analog signal.…,…,,,,,,……,,,…,,,…,…,…,…,,…7 23 System clock….......………….7 2.3. 1 System Interface signal 2.3.2 PCI Express Interface 8 2.3.3 USB Interface 2.3.4 SPl Interface 3. Register Information…,.,,… …:12 3.1 Register Attributes…… 12 3.2PC| Configuration Space….…,…,… …13 3.2.1 PCI Type o Configuration space header 3.2.1. 1 Vendor Id Register Device ID Register 15 Command Register 3. 2.1.4 Status Register 16 3. 2.1.5 Revision ID Register 17 Class Code Register 17 3. 2.1.7 Cache Line Size Register 3. 2.1.8 Latency Timer Register 3. 2.1.9 Header Type Register. 3. 2.1.10 BIST Register... 18 3.2.1. 11 Base Address register #O 18 3.2.1. 12 Base Address Register #1 19 Subsystem Vendor iD Register 19 3. 2.1.14 Subsystem iD Register 19 3.2.1. 15 Capabilities Pointer Register 3. 2.1.16 Interrupt Line Register .. 3. 2.1.17 Interrupt Pin Register 3. 2.1.18 Min_Gnt Register 3.2.1. 19 Max_LaT Register 3. 2.1. 20 Serial Bus Release Number Register(SBRN) 20 3. 2.1.21 Frame Length Adjustment Register(FLADJ) 21 322 PCI Power Management Capabilities…… 3. 2.2. 1 Capabilities List Register Power Management Capabilities Register(PMC) Power Management Status/Control Register(PMSC) 3.2.3 MSI Capabilities..... 25 3. 2.3. 1 Capabilities List Register for Ms Message Control for MsI 3. 2.3. 3 Message Address for MSI 3. 2.3.4 Message Upper Address for MsI 3. 2.3.5 Message Data for MsI 26 Mask Bits for MSI Pending Bits for MsI 26 3.2.4 MSI-X Capabilities 27 3241 Capabilities List Register for Ms|X…… 27 Message Control for MSI-X 3. 2.4.3 Table Offset /Table biR for MSI-X 27 3.2.4. 4 PBA Offset for MsI-X 3.2.5 PCI Express Extended Capabilities 3. 2.5.1 PCI Express Capabilities List Register 29 PCI Express Capabilities Register 3. 2.5.3 Device Capabilities Register 3. 2.5. 4 Device Control Register Device Status Register 31 Link Capabilities Register 3. 2.5.7 Link Control Register . 3. 2.5.8 Link Status Register. 34 3.2.5. 9 Device Capabilities 2 Register........ 3.2.5. 10 Device Control 2 Register 34 3. 2.5.11 Device Status 2 Register 3. 2.5. 12 Link Capabilities 2 Register 3. 2.5. 13 Link Control 2 Register 3. 2.5. 14 Link Status 2 Register 3.2.6 RENESAS Specific Registers 326.1 FW Version Register….,……… 37 PHY Control o Register. .37 PHY Control 1 Register 3. 2.6.4 PHY Control 2 Register 3. 2.6.5 Host Controller Configuration(HCConfiguration) Register 3266 External ROM Information Register………… 42 3.26.7 External ROM Configuration Register.……… FW Download Control and Status Register 3.2.6. 9 EXternal ROM Access Control and Status Register 43 DATAO Reqister 3.2.6. 11 DATA1 Register 45 3.2.7 Advanced Error Reporting Capabilities 3. 2.7.1 Advanced Error Reporting Enhanced Capability Header Register Uncorrectable Error Status Register 3. 2.7.3 Uncorrectable Error Mask Register 47 3. 2.7.4 Uncorrectable Error Severity Register Correctable Error Status Register Correctable error mask register 48 3. 2.7.7 Advanced Error Capabilities and Control Register 49 3. 2.7.8 Header Log Register 3.2.8 Device Serial Number Enhanced Capability 50 3.2.8. 1 Device Serial Number Enhanced Capability Header Register 50 3. 2.8.2 Serial Number Register.. 50 3.2.9 Latency Tolerance Reporting(LTR) Capability 51 3. 2.9. 1 LTR EXtended Capability Header Register 51 Max Snoop latency register 51 3. 2.9.3 Max No-Snoop Latency Register 51 3. 3 Host Controller Capability Register 52 3.3. 1 Capability Registers Length(CAPLENGTH) 3.3.2 Host Controller Interface Version Number(HcIVERSION 3.3.3 Structural Parameters 1(HCSPARAMS1) 53 3.3. 4 Structural Parameters 2(HCSPARAMS2) 3.3.5 Structural Parameters 3(HCSPARAMS3) 3.3.6 Capability Parameters(HCCPARAMs) 54 3.3.7 Doorbell Offset(DBOFF) 3.3.8 Runtime Register Space Offset(RTSOFF 34 Host contro| er Operational Registers.,…,,…,,…,,……,,,57 3.4.1 USB Command Register (USBCMD) 3.4.2 USB Status Register(USBSTS ∴60 3.4.3 Page Size Register(Pagesize) 3.4.4 Device Notification Control Register(DNCTRL) 3.4.5 Command Ring Control Register (CRCR) 3.4.6 Device Context Base Address Array Pointer Register(DCBAAP) 3.4.7 Configure Register(CONFIG) 3.4.8 Host Controller Port Register Set.... 3. 4.8.1 Port Status and Control Register(PORTS 67 3. 4.8.2 Port PM Status and Control Register (PORTPMSC) USB3 Protocol PoRTPMsC definition 3. 48 4 USB2 Protocol portpmsc definition Port Link Info Register(PORTLD) 176 3.5 Host Controller Runtime Registers ame m.ma..mma. 77 3.51 Microframe Index Register( MEINDEⅩ)…… ∴77 3.5.2 Interrupter Register Set Interrupter Management Register(IMAN) Interrupter Moderation Register(IMOD) Event Ring Segment Table Size Register(ERSTSZ 1 Event Ring Segment Table Base Address Register (ERSTBA) 80 Event Ring Dequeue Pointer Register(ERDP) 81 3.6 Doorbell Registers. 282 3.7 xHCI Extended capabilities 3.7.1 USB Legacy Support capability USB Legacy Support Capability( USBLEGSUP.……… 83 37.1.2 USB Legacy Support Control/ Status( USBLEGCTLSTS)…………84 3.7.2xHc| Supported Protocol Capability…… USB 3.0 Supported Protocol Capability USB 2.0 Supported Protocol Capability 87 3.7.3 Debug Capability 3.7.3. 1 Debug Capability ID Register.. Debug Capability doorbell register 90 3.7.3. 3 Debug Capability Event Ring Segment Table Size Register 90 3.7. 3.4 Debug Capability Event Ring Segment Table Base Address Register ...........90 Debug Capability Event Ring Dequeue Pointer Register 91 Debug Capability Event Ring Dequeue Pointer Register 91 3.7. 3.7 Debug Capability Status Register 93 3.7. 3.8 Debug Capability port Status and Control Register 3.7.3. 9 Debug Capability Context Pointer Register 3.7.3. 10 Debug Capability Device Descriptor Info Register 1 Debug Capability Device Descriptor Info Register2……… 96 3.8 MSI-X/PBA Table 98 3.8.1 Message Address for MSI-X Table 3.8.2 Message Upper Address for MSl-X Table 3.8. 3 Message Data for MSI-x 3. 8. 4 Vector control for msl-x 3.8.5 Pending Bits for MS|- X PBA Entries…… 4. Power Management 100 4.1 Power Management States 10 4.1.1 PCI Express Link State Power Management (L-States) 100 4.1.2 PCI Express Device Power Management States(D-States) 101 4.1.3 CLKREQ# Signal …101 4.1. 4 Summary of PCI Express Power Management States 4.2 Power Management Event(PME) Mechanism…… 103 4.2.1 PME support 103 4.2.2 Pin configuration for supporting PME generation from D3cold 103 4.2.3 Timing Diagram for PME 104 4. 2. 4 Wakeup Events 106 4.3 Control for System Clock Operation 107 4.3.1 Clock system 107 4.4 Latency Tolerance Reporting(LTR) mechanism.. 108 4.4.1 Timing of sending LTR message 5. How to connect to External e| ements……109 5.1 Handling Unused Pins...............-. 109 5.2 USB Port Connection 面国国重面日 110 5.3 Analog Circuit Connection 114 5.4 Crystal Connection.…,,…,…,,,,…,,…,…,……,,…,…,…,…,…,……,115 5.5 External serial ROM Connection 116 56Pc| Express Interface Connection…,…,,…,…,…,,……,…,,118 5.7 SMIB/SMI Interface Connection 119 6. How to access external rom 120 61 Access Externa| ROM Registers,,…,…,…,…,…,…,…,,…,120 6.2 Access External RoM mmmmmmmm. 122 6.2. 1 How to write fw to extenal rom Outline Sequence to write the FW(External ROM data of uPD720201 and PD720202 122 6.2.2 How to read rom Data from External ro 123 62.2.10 utline∴ 123 6. 2.2.2 Sequence to read External ROM data from External ROM... 123 623 How to erase the data of the whole chip to be“b"( Chip erase)……,,123 62.3.1ou 123 6. 2.3.2 Sequence for Chip Erase 123 6.3 Data Format 124 6. 3. 1 Firmware 124 6.3.2 Vendor Specific Configuration Data Block 125 6.3.2. 1 Data Format ∴125 6.3. 2.2 Address map for Vendor Specific Configuration Block 125 External RoM Data 127 6.3.3 CRC16 calculation 128 6.3.4 External ROM Data format 129 First External ROM Image Data Block of Figure 6-4 129 Second External ROM Image Data Block of Figure 6-4 129 Loading the FW from the External ROM 129 7. FW Download interface 131 7.1 How to Download a Firmware into APD720201/uPD720202 131 7.1.1 FW download registers 131 7.1.2 Outline of fw download sequences 131 7.1.3 Fw download sequences .131 8. Battery Charging Function 133 8. 1 Features 133 8. 2 Battery Charging Mode 国■ 133 8.3 How to set Up…,,,,,…,…,,,…,,,,…,,,…,…,…,,…134 8.3.1 HW configuration requirement..….… .134

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