IMXRT1020RM（参考手册）_nxpi:mxrt1021开发手册资源-CSDN文库

RT1020

5星 · 超过95%的资源需积分: 50 16 浏览量 2019-03-19 01:49:13 上传评论收藏 26.43MB PDF 举报

资源推荐

资源详情

资源评论

i.MX RT1020 Processor Reference

Manual

Document Number: IMXRT1020RM

Rev. 0, 06/2018

Contents

Section number Title Page

Chapter 1

Introduction

1.1 About This Document...................................................................................................................................................181

1.1.1 Audience...................................................................................................................................................... 181

1.1.2 Organization.................................................................................................................................................181

1.1.3 Suggested Reading.......................................................................................................................................181

1.1.3.1 General Information...................................................................................................................182

1.1.3.2 Related Documentation..............................................................................................................182

1.1.4 Conventions................................................................................................................................................. 182

1.1.5 Register Access............................................................................................................................................184

1.1.5.1 Register Diagram Field Access Type Legend............................................................................184

1.1.5.2 Register Macro Usage................................................................................................................184

1.1.6 Signal Conventions...................................................................................................................................... 186

1.1.7 Acronyms and Abbreviations.......................................................................................................................186

1.2 Introduction...................................................................................................................................................................189

1.2.1 Block Diagram............................................................................................................................................. 189

1.3 Features.........................................................................................................................................................................190

1.4 Target Applications.......................................................................................................................................................192

1.5 Endianness Support.......................................................................................................................................................192

Chapter 2

Memory Maps

2.1 Memory system overview.............................................................................................................................................193

2.2 ARM Platform Memory Map....................................................................................................................................... 193

Chapter 3

Interrupts, DMA Events, and XBAR Assignments

3.1 Overview.......................................................................................................................................................................201

3.2 CM7 interrupts..............................................................................................................................................................201

3.3 DMA Mux.....................................................................................................................................................................208

i.MX RT1020 Processor Reference Manual, Rev. 0, 06/2018

NXP Semiconductors 3

Section number Title Page

3.4 XBAR Resource Assignments......................................................................................................................................214

Chapter 4

External Signals and Pin Multiplexing

4.1 Overview.......................................................................................................................................................................223

4.1.1 Muxing Options........................................................................................................................................... 223

Chapter 5

Fusemap

5.1 Boot Fusemap............................................................................................................................................................... 243

5.2 Lock Fusemap...............................................................................................................................................................254

5.3 Fusemap Descriptions Table.........................................................................................................................................254

Chapter 6

External Memory Controllers

6.1 Overview.......................................................................................................................................................................269

6.2 Smart External Memory Controller (SEMC) Overview...............................................................................................269

6.3 eMMC/eSD/SDIO.........................................................................................................................................................271

6.4 Quad Serial Peripheral Interface...................................................................................................................................272

Chapter 7

System Debug

7.1 Overview.......................................................................................................................................................................273

7.2 Chip and ARM Platform Debug Architecture.............................................................................................................. 273

7.2.1 Debug Features............................................................................................................................................ 274

7.2.2 Debug system components...........................................................................................................................274

7.2.2.1 AMBA Trace Bus (ATB)...........................................................................................................274

7.2.2.2 CoreSight trace port interface (TPIU)........................................................................................275

7.2.2.3 Embedded Trace Macrocell (ETM)........................................................................................... 276

7.2.2.4 Instrumentation Trace Macrocell...............................................................................................276

7.2.3 Chip-Specific SJC Features......................................................................................................................... 277

7.2.3.1 JTAG Disable Mode.................................................................................................................. 277

7.2.3.2 JTAG ID.....................................................................................................................................277

7.2.4 System JTAG controller main features........................................................................................................278

i.MX RT1020 Processor Reference Manual, Rev. 0, 06/2018

4 NXP Semiconductors

Section number Title Page

7.2.5 SJC TAP Port...............................................................................................................................................278

7.2.6 SJC main blocks...........................................................................................................................................278

7.3 Miscellaneous............................................................................................................................................................... 279

7.3.1 Clock/Reset/Power.......................................................................................................................................279

7.4 Supported tools............................................................................................................................................................. 279

Chapter 8

System Boot

8.1 Chip-specific Boot Information.................................................................................................................................... 281

8.2 Overview.......................................................................................................................................................................284

8.3 Boot modes................................................................................................................................................................... 285

8.3.1 Boot mode pin settings.................................................................................................................................286

8.3.2 High-level boot sequence.............................................................................................................................286

8.3.3 Boot From Fuses mode (BOOT_MODE[1:0] = 00b)..................................................................................287

8.3.4 Serial Downloader (BOOT_MODE[1:0] = 01b)......................................................................................... 288

8.3.5 Internal Boot mode (BOOT_MODE[1:0] = 0b10)...................................................................................... 288

8.3.6 Boot security settings...................................................................................................................................289

8.4 Device configuration.....................................................................................................................................................290

8.4.1 Boot eFUSE descriptions.............................................................................................................................290

8.4.2 GPIO boot overrides.................................................................................................................................... 291

8.4.3 Device Configuration Data (DCD).............................................................................................................. 292

8.5 Device initialization......................................................................................................................................................292

8.5.1 Internal ROM/RAM memory map...............................................................................................................293

8.5.2 Boot block activation .................................................................................................................................. 293

8.5.3 Clocks at boot time...................................................................................................................................... 294

8.5.4 Enabling Caches...........................................................................................................................................296

8.5.5 Exception handling...................................................................................................................................... 296

8.5.6 Interrupt handling during boot..................................................................................................................... 297

8.5.7 Persistent bits............................................................................................................................................... 297

8.6 Boot devices (internal boot)..........................................................................................................................................297

i.MX RT1020 Processor Reference Manual, Rev. 0, 06/2018

NXP Semiconductors 5