PCI EXPRESS BASE SPECIFICATION, REV. 4.0 VERSION 0.3
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Update Ordering and Granularity Observed by a Read Transaction ................ 145 2.4.2.
Update Ordering and Granularity Provided by a Write Transaction ................ 146 2.4.3.
2.5. VIRTUAL CHANNEL (VC) MECHANISM ........................................................................ 147
Virtual Channel Identification (VC ID) .............................................................. 149 2.5.1.
TC to VC Mapping .............................................................................................. 150 2.5.2.
VC and TC Rules ................................................................................................. 151 2.5.3.
2.6. ORDERING AND RECEIVE BUFFER FLOW CONTROL ..................................................... 152
Flow Control Rules ............................................................................................. 153 2.6.1.
2.7. DATA INTEGRITY ......................................................................................................... 164
ECRC Rules ........................................................................................................ 165 2.7.1.
Error Forwarding ............................................................................................... 169 2.7.2.
2.8. COMPLETION TIMEOUT MECHANISM ........................................................................... 171
2.9. LINK STATUS DEPENDENCIES ...................................................................................... 172
Transaction Layer Behavior in DL_Down Status ............................................... 172 2.9.1.
Transaction Layer Behavior in DL_Up Status ................................................... 173 2.9.2.
Transaction Layer Behavior During Downstream Port Containment ............... 174 2.9.3.
3. DATA LINK LAYER SPECIFICATION ...................................................................... 176
3.1. DATA LINK LAYER OVERVIEW .................................................................................... 176
3.2. DATA LINK CONTROL AND MANAGEMENT STATE MACHINE ...................................... 178
Data Link Control and Management State Machine Rules ................................ 179 3.2.1.
3.3.
FLOW CONTROL INITIALIZATION PROTOCOL ............................................................... 181
Flow Control Initialization State Machine Rules ............................................... 182 3.3.1.
3.4. DATA LINK LAYER PACKETS (DLLPS) ........................................................................ 185
Data Link Layer Packet Rules ............................................................................ 185 3.4.1.
3.5. DATA INTEGRITY ......................................................................................................... 190
Introduction......................................................................................................... 190 3.5.1.
LCRC, Sequence Number, and Retry Management (TLP Transmitter).............. 190 3.5.2.
LCRC and Sequence Number (TLP Receiver) .................................................... 203 3.5.3.
4. PHYSICAL LAYER SPECIFICATION ........................................................................ 213
4.1. INTRODUCTION ............................................................................................................ 213
4.2. LOGICAL SUB-BLOCK ................................................................................................... 213
Encoding for 2.5 GT/s and 5.0 GT/s Data Rates ................................................ 214 4.2.1.
Encoding for 8.0 GT/s and Higher Data Rates................................................... 222 4.2.2.
Link Equalization Procedure for 8.0 GT/s and Higher Data Rates ................... 241 4.2.3.
Link Initialization and Training .......................................................................... 251 4.2.4.
Link Training and Status State Machine (LTSSM) Descriptions ........................ 270 4.2.5.
Link Training and Status State Rules .................................................................. 273 4.2.6.
Clock Tolerance Compensation .......................................................................... 342 4.2.7.
Compliance Pattern in 8b/10b Encoding ............................................................ 347 4.2.8.
Modified Compliance Pattern in 8b/10b Encoding ............................................ 348 4.2.9.
Compliance Pattern in 128b/130b Encoding ...................................................... 350 4.2.10.
Modified Compliance Pattern in 128b/130b Encoding ...................................... 352 4.2.11.
5. POWER MANAGEMENT .............................................................................................. 353
5.1. OVERVIEW ................................................................................................................... 353
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