RapidIO Trade Association
Rev. 2.0.1, 03/2008
© Copyright RapidIO Trade Association
RapidIO
TM
Interconnect Specification
Part 6: LP-Serial Physical
Layer Specification
RapidIO Trade Association
NO WARRANTY.THE RAPIDIO TRADE ASSOCIATION PUBLISHES THE SPECIFICATION “AS IS”. THE RAPIDIO TRADE
ASSOCIATION MAKES NO WARRANTY, REPRESENTATION OR COVENANT, EXPRESS OR IMPLIED, OF ANY KIND
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SUCH USE OF THE SPECIFICATION.
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Revision History
Revision Description Date
1.1 First release 12/17/2001
1.2 Technical changes: incorporate Rev. 1.1 errata rev. 1.1.1, errata 3 06/26/2002
1.3 Technical changes: incorporate Rev 1.2 errata 1 as applicable,
the following errata showings:
03-03-00004.002, 03-07-00002.001, 03-12-00000.002, 03-12-00002.004,
04-02-00000.001, 04-05-00000.003, 04-05-00006.002 (partial), 04-05-00007.001
and the following new features showings:
02-03-0003.004, 02-06-00001.004, 04-08-00013.002, 04-09-00022.002
Converted to ISO-friendly templates
02/23/2005
1.3 Removed confidentiality markings for public release 06/07/2005
2.0 Significant editorial changes
Technical changes: errata showings 04-11-00031.001, 06-04-00000.003,
06-07-00001.001, 07-03-00000.002, 07-03-00001.001
new features showings 05-04-00001.005, 05-04-00003.004, new speed bin and width
definitions with supporting protocol
06/14/2007
2.0.1 Very minor editorial changes 08/29/2007
2.0.1 Removed confidentiality markings for public release 03/06/2008
Table of Contents
RapidIO Trade Association 3
RapidIO Part 6: LP-Serial Physical Layer Specification Rev. 2.0
Chapter 1 Overview
1.1 Introduction........................................................................................................... 23
1.2 Contents ................................................................................................................ 24
1.3 Terminology.......................................................................................................... 25
1.4 Conventions .......................................................................................................... 25
Chapter 2 Packets
2.1 Introduction........................................................................................................... 27
2.2 Packet Field Definitions........................................................................................ 27
2.3 Packet Format ....................................................................................................... 29
2.4 Packet Protection .................................................................................................. 29
2.4.1 Packet CRC Operation...................................................................................... 30
2.4.2 CRC-16 Code.................................................................................................... 32
2.5 Maximum Packet Size .......................................................................................... 34
Chapter 3 Control Symbols
3.1 Introduction........................................................................................................... 35
3.2 Control Symbol Field Definitions......................................................................... 35
3.3 Control Symbol Format ........................................................................................ 36
3.4 Stype0 Control Symbols....................................................................................... 37
3.4.1 Packet-Accepted Control Symbol..................................................................... 39
3.4.2 Packet-Retry Control Symbol........................................................................... 39
3.4.3 Packet-Not-Accepted Control Symbol ............................................................. 40
3.4.4 Status Control Symbol...................................................................................... 41
3.4.5 VC-Status Control Symbol............................................................................... 41
3.4.6 Link-Response Control Symbol ....................................................................... 42
3.5 Stype1 Control Symbols....................................................................................... 43
3.5.1 Start-of-Packet Control Symbol........................................................................ 44
3.5.2 Stomp Control Symbol ..................................................................................... 44
3.5.3 End-of-Packet Control Symbol......................................................................... 45
3.5.4 Restart-From-Retry Control Symbol ................................................................ 45
3.5.5 Link-Request Control Symbol.......................................................................... 45
3.5.5.1 Enter-Loopback Command........................................................................... 46
3.5.5.2 Exit-Loopback Command............................................................................. 46
3.5.5.3 Reset-Device Command............................................................................... 47
3.5.5.4 Input-Status Command................................................................................. 47
3.5.6 Multicast-Event Control Symbol...................................................................... 47
3.6 Control Symbol Protection ................................................................................... 48
3.6.1 CRC-5 Code...................................................................................................... 48
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Table of Contents
RapidIO Part 6: LP-Serial Physical Layer Specification Rev. 2.0
3.6.2 CRC-5 Parallel Code Generation...................................................................... 48
3.6.3 CRC-13 Code.................................................................................................... 50
3.6.4 CRC-13 Parallel Code Generation.................................................................... 50
Chapter 4 PCS and PMA Layers
4.1 Introduction........................................................................................................... 53
4.2 PCS Layer Functions ............................................................................................ 53
4.3 PMA Layer Functions........................................................................................... 54
4.4 Definitions ............................................................................................................ 54
4.5 8B/10B Transmission Code.................................................................................. 55
4.5.1 Character and Code-Group Notation................................................................ 56
4.5.2 Running Disparity............................................................................................. 57
4.5.3 Running Disparity Rules................................................................................... 57
4.5.4 8B/10B Encoding.............................................................................................. 58
4.5.5 Transmission Order........................................................................................... 58
4.5.6 8B/10B Decoding ............................................................................................. 59
4.5.7 Special Characters and Columns ...................................................................... 68
4.5.7.1 Packet Delimiter Control Symbol (/PD/)...................................................... 68
4.5.7.2 Start of Control Symbol (/SC/)..................................................................... 69
4.5.7.3 Idle (/I/)......................................................................................................... 69
4.5.7.4 Sync (/K/)...................................................................................................... 69
4.5.7.5 Skip (/R/) ...................................................................................................... 69
4.5.7.6 Align (/A/) .................................................................................................... 69
4.5.7.7 Mark (/M/) .................................................................................................... 69
4.5.8 Effect of Single Bit Code-Group Errors ........................................................... 69
4.6 LP-Serial Link Widths.......................................................................................... 70
4.7 Idle Sequence........................................................................................................ 71
4.7.1 Clock Compensation Sequence ........................................................................ 72
4.7.2 Idle Sequence 1 (IDLE1).................................................................................. 72
4.7.3 Idle Sequence 1 Generation .............................................................................. 73
4.7.4 Idle Sequence 2 (IDLE2).................................................................................. 74
4.7.4.1 Idle Frame..................................................................................................... 75
4.7.4.1.1 IDLE Sequence 2 Random Data Field ..................................................... 75
4.7.4.1.2 IDLE Sequence 2 CS Field Marker.......................................................... 76
4.7.4.1.3 IDLE2 Command and Status Field (CS field).......................................... 78
4.7.4.1.4 IDLE2 CS Field Use................................................................................. 80
4.7.5 Idle Sequence Selection.................................................................................... 83
4.8 Scrambling............................................................................................................ 84
4.8.1 Scrambling Rules.............................................................................................. 84
4.8.2 Descrambler Synchronization........................................................................... 86
4.8.3 Descrambler Synchronization Verification ...................................................... 86
4.9 1x Mode Transmission Rules ............................................................................... 88
4.9.1 1x Ports ............................................................................................................. 88
4.9.2 Nx Ports Operating in 1x Mode........................................................................ 90
4.10 Nx Link Striping and Transmission Rules............................................................ 91
RapidIO Part 6: LP-Serial Physical Layer Specification Rev. 2.0
Table of Contents
RapidIO Trade Association 5
4.11 Retimers and Repeaters ........................................................................................ 93
4.11.1 Retimers............................................................................................................ 94
4.11.2 Repeaters........................................................................................................... 94
4.12 Port Initialization .................................................................................................. 95
4.12.1 1x Mode Initialization....................................................................................... 95
4.12.2 1x/Nx Mode Initialization................................................................................. 95
4.12.3 Baud Rate Discovery ........................................................................................ 95
4.12.4 State Machines.................................................................................................. 97
4.12.4.1 State Machine Conventions.......................................................................... 97
4.12.4.2 State Machine Variables and Functions ....................................................... 97
4.12.4.3 Lane Synchronization State Machine......................................................... 101
4.12.4.4 Lane Alignment State Machine .................................................................. 104
4.12.4.5 1x Mode Initialization State Machine......................................................... 106
4.12.4.6 1x/Nx Mode Initialization State Machine................................................... 107
Chapter 5 LP-Serial Protocol
5.1 Introduction......................................................................................................... 115
5.2 Packet Exchange Protocol .................................................................................. 115
5.3 Traffic types........................................................................................................ 116
5.4 Virtual Channels ................................................................................................. 117
5.4.1 Virtual channel 0 (VC0) ................................................................................. 117
5.4.2 Virtual Channels 1-8 (VC1-8) ........................................................................ 117
5.4.3 Virtual Channel Utilization............................................................................. 118
5.5 Control Symbols ................................................................................................. 118
5.5.1 Control Symbol Selection............................................................................... 118
5.5.2 Control Symbol Delimiting ............................................................................ 119
5.5.3 Control Symbol Use ....................................................................................... 119
5.5.3.1 Link Initialization ....................................................................................... 119
5.5.3.2 Buffer Status Maintenance ......................................................................... 120
5.5.3.3 Embedded Control Symbols....................................................................... 121
5.5.3.4 Multicast-Event Control Symbols .............................................................. 121
5.6 Packets ................................................................................................................ 122
5.6.1 Packet Delimiting ........................................................................................... 122
5.6.1.1 Packet Start................................................................................................. 122
5.6.1.2 Packet Termination..................................................................................... 123
5.6.2 Acknowledgment Identifier............................................................................ 123
5.6.3 Packet Priority and Transaction Request Flows ............................................. 123
5.7 Link Maintenance Protocol................................................................................. 125
5.8 Packet Transmission Protocol............................................................................. 126
5.9 Flow Control....................................................................................................... 128
5.9.1 Receiver-Controlled Flow Control ................................................................. 128
5.9.1.1 Reliable Traffic VC Receivers.................................................................... 129
5.9.1.2 Continuous Traffic VC Receivers .............................................................. 129
5.9.1.3 Single VC Retry Protocol........................................................................... 129
5.9.1.4 Input Retry-Stopped Recovery Process...................................................... 131
