FPGA based data acquisition and analysis system
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2015-10-29
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FPGA based data acquisition and analysis system
S
antosh Gujare
, Gaurav Jagtap, Damayanti Gharpure
, S. Ananthakrishnan
Department of Electronic Science,
University of Pune,
Pune, 4011007, India.
E-mail: santosh@electronics.unipune.ac.in
, gnj_rflab@electronics.unipune.ac.in
A
bstract— This paper presents prototype design of the FPGA
b
ased digital back-end for data acquisition and processing.
The system consists of acquiring 1024 samples of data. The
stored data is input to FFT core for data analysis. An RS 232
port has been implemented to aid in testing and debugging the
system. Various modules are developed in VHDL and
integrated to realize the complete system. The design is
implemented and tested on SPARTAN 3E platform.
Keywords- FPGA, FFT, SPI, ADC.
I. IN
TRODUCTION
I
n recent years, it is evident that the latest generation of
FPGA devices is extensively used in digital back-ends in
Radio Astronomy applications. Due to flexibility in design,
high processing power, large gate counts, integrated
resources like on-chip Block RAMs and high clocking
speeds, digital designers prefer FPGAs over other devices.
In applications like Radio Astronomy, multichannel high
speed runtime processing is one of the necessary pre-
requisites which can be realized with ease, using FPGA
based design. Platform independent hardware description
languages like VHDL, Verilog, well developed synthesis
and implementation tools are major advantages of designs
based on FPGAs.
This paper deals with designing a data acquisition system
(DAQ) for low-frequency radio observations. The present
work deals with a preliminary design which works at
1.5MSPS and which can be easily scaled to a high sampling
rate. Considering huge volumes of data generated,
compressing the data by sorting the data into frequency bins
was also taken up. Fast Fourier Transform technique plays a
dual role of transforming time domain signal into its
frequency domain components as well as reducing the
output data volume effectively by sorting the data into
individual frequency bins.
II. SYSTEM ARCHITECTURE
A. Overview
As a preliminary experiment a two channel Data acquisition
system is realized using the Spartan board available. The
prototype design is implemented and tested using the
Spartan®-3E FPGA Starter Kit board [2]. Top level system
architecture, consists of signal conditioning circuit, Analog
to Digital Converter (ADC), SPARTAN 3E FPGA and data
transfer mechanism using RS 232. The system acquires the
analog signal using on board ADC and digital processing is
done using FPGA.
The crystal frequency available on SPARTAN 3E board is
50MHz. The maximum speed possible for the onboard ADC
is limited to 1.5MSPS. The Serial Peripheral Interface (SPI)
based serial ADC is driven by the crystal clock and serial
data output consisting of 34 clock cycles limits the overall
speed of the system. 1024 byte of data is acquired and
stored in the block Ram of the FPGA. The stored data is
input to the FFT core. The FFT output data in the format of
27 bit signed number is converted into 32 bit signed number
and loaded in the Block RAM. The data from block RAM
is transferred to host PC using serial interface. A program
was written in C on the Host PC to read the data and the
output was plotted using MATLAB. The block diagram
shown in Fig.1 gives brief overview of the design. Pre-Amp
and ADC communicate with FPGA using SPI protocol. The
FPGA contains on chip Block RAM interfaced with FFT
core and control mechanism used to synchronize data
processing and data transfer tasks. Modules have been
developed to implement SPI as well as serial port interfaces
F
ig. 1 Block Diagram
The ADC was initially calibrated for DC inputs by
observing the output on led’s provided on the Board as well
as oscilloscope. Then, analog inputs were fed and the
digitized data was logged into the block RAM. For the
purpose of debugging, the data from the block RAM was
read through RS 232 port to PC with the help of onboard
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