SSD1316
Rev 1.2
P 3/63
Nov 2013
Solomon Systech
CONTENTS
1 GENERAL DESCRIPTION ........................................................................................................ 7
2 FEATURES.................................................................................................................................... 7
3 ORDERING INFORMATION .................................................................................................... 7
4 BLOCK DIAGRAM ..................................................................................................................... 8
5 DIE PAD FLOOR PLAN ............................................................................................................. 9
6 PIN DESCRIPTION ................................................................................................................... 11
7 FUNCTIONAL BLOCK DESCRIPTIONS ............................................................................. 13
7.1
MCU
I
NTERFACE SELECTION
............................................................................................................................... 13
7.1.1
MCU Parallel 6800-series Interface ........................................................................................................... 13
7.1.2
MCU Parallel 8080-series Interface ........................................................................................................... 14
7.1.3
MCU Serial Interface (4-wire SPI) ............................................................................................................. 15
7.1.4
MCU Serial Interface (3-wire SPI) ............................................................................................................. 16
7.1.5
MCU I
2
C Interface ...................................................................................................................................... 17
7.2
C
OMMAND
D
ECODER
.......................................................................................................................................... 20
7.3
O
SCILLATOR
C
IRCUIT AND
D
ISPLAY
T
IME
G
ENERATOR
...................................................................................... 20
7.4
FR
SYNCHRONIZATION
........................................................................................................................................ 21
7.5
R
ESET
C
IRCUIT
.................................................................................................................................................... 21
7.6
S
EGMENT
D
RIVERS
/
C
OMMON
D
RIVERS
............................................................................................................. 22
7.7
G
RAPHIC
D
ISPLAY
D
ATA
RAM
(GDDRAM) ...................................................................................................... 23
7.8
SEG/COM
D
RIVING BLOCK
................................................................................................................................ 24
7.9
P
OWER
ON
AND
OFF
SEQUENCE
......................................................................................................................... 25
7.9.1
Power ON and OFF sequence with External V
CC
....................................................................................... 25
7.9.2
Power ON and OFF sequence with Charge Pump Application .................................................................. 26
7.10
C
HARGE
P
UMP
R
EGULATOR
................................................................................................................................ 27
8 COMMAND TABLE .................................................................................................................. 27
8.1
D
ATA
R
EAD
/
W
RITE
........................................................................................................................................... 37
9 COMMAND DESCRIPTIONS .................................................................................................. 38
9.1
F
UNDAMENTAL
C
OMMAND
................................................................................................................................. 38
9.1.1
Set Lower Column Start Address for Page Addressing Mode (00h~0Fh) .................................................. 38
9.1.2
Set Higher Column Start Address for Page Addressing Mode (10h~17h) .................................................. 38
9.1.3
Set Memory Addressing Mode (20h) ........................................................................................................... 38
9.1.4
Set Column Address (21h)........................................................................................................................... 39
9.1.5
Set Page Address (22h) ............................................................................................................................... 40
9.1.6
Set Display Start Line (40h~66h) ................................................................................................................ 40
9.1.7
Set Contrast Control (81h) .......................................................................................................................... 40
9.1.8
Set Segment Re-map (A0h/A1h) .................................................................................................................. 40
9.1.9
Entire Display ON (A4h/A5h) ................................................................................................................... 41
9.1.10
Set Normal/Inverse Display (A6h/A7h) ....................................................................................................... 41
9.1.11
Set Multiplex Ratio (A8h) ............................................................................................................................ 41
9.1.12
External or Internal VCOMH Selection / External or internal IREF Selection (ADh) ............................... 41
9.1.13
Set Display ON/OFF (AEh/AFh) ................................................................................................................ 41
9.1.14
Set Page Start Address for Page Addressing Mode (B0h~B4h) .................................................................. 41
9.1.15
Set COM Output Scan Direction (C0h/C8h) ............................................................................................... 42
9.1.16
Set Display Offset (D3h) ............................................................................................................................. 42
9.1.17
Set Display Clock Divide Ratio/ Oscillator Frequency (D5h) .................................................................... 45
9.1.18
Set Pre-charge Period (D9h) ...................................................................................................................... 45
9.1.19
Set COM Pins Hardware Configuration (DAh) .......................................................................................... 45