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directory based cache coherency
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directory based cache coherency,内存一致性
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http://www.csg.csail.mit.edu/6.823
Joel Emer
Computer Science and Artificial Intelligence Lab
M.I.T.
Directory-Based Cache Coherence
1
Sanchez & Emer
http://www.csg.csail.mit.edu/6.823
Maintaining Cache Coherence
It is sufficient to have hardware such that
• only one processor at a time has write permission
for a location
• no processor can load a stale copy of the location
after a write
Þ Α correct approach could be:
write request:
The address is invalidated in all other caches before
the write is performed
read request:
If a dirty copy is found in some cache, a write-back
is performed before the memory is read
April 4, 2016
L16-2
Sanchez & Emer
http://www.csg.csail.mit.edu/6.823
Directory-Based Coherence
(Censier and Feautrier, 1978)
• Snoopy schemes broadcast
requests over memory bus
• Difficult to scale to large
numbers of processors
• Requires additional
bandwidth to cache tags for
snoop requests
• Directory schemes send
messages to only those caches
that might have the line
• Can scale to large numbers of
processors
• Requires extra directory
storage to track possible
sharers
$
P
$
P
$
P
$
P
Bus
Mem.
Snoopy Protocols
$
P
$
P
$
P
$
P
Dir.
Interconnect
Network
Mem.
Directory Protocols
April 4, 2016
L16-3
Sanchez & Emer
An MSI Directory Protocol
• Cache states: Modified (M) / Shared (S) / Invalid (I)
• Directory states:
– Uncached (Un): No sharers
– Shared (Sh): One or more sharers with read permission (S)
– Exclusive (Ex): A single sharer with read & write permissions (M)
• Transient states not drawn for clarity; for now,
assume no racing requests
http://www.csg.csail.mit.edu/6.823
Core 0
Main Memory
Cache 0
Core N
Cache N
Tag State Data
Tag State DataTag State Data
Directory
Tag State Sharers
…
April 4, 2016
L16-4
Sanchez & Emer
MSI Protocol: Caches (1/3)
http://www.csg.csail.mit.edu/6.823
M
S
I
PrWr / ExReq
Transitions initiated by processor accesses:
PrRd / ShReq
PrWr /
ExReq
PrRd / --
PrRd / --
PrWr / --
Actions
Processor Read (PrRd)
Processor Write (PrWr)
Shared Request
(ShReq)
Exclusive Request
(ExReq)
April 4, 2016
L16-5
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