3
3. Pin Description
Input Parts
Signals I/O
Pin
Number
Connected
with
Description
Select the MPU interface mode as listed below
IM0(ID)
IM1 IM2 IM3 MPU interface mode DB pins
0 0 0 0 Setting invalid -
1 0 0 0 Setting invalid -
0 1 0 0 16-bit bus interface,80-system DB17-10,8-1
1 1 0 0 8-bit bus interface , 80-system DB17-10
ID 0 1 0 Serial data transfer interface DB1-0
* 1 1 0 Setting invalid -
0 0 0 1 Setting invalid -
1 0 0 1 Setting invalid -
0 1 0 1 18-bit bus interface,80-system DB17-0
1 1 0 1 9-bit bus interface, 80-system DB17-9
* * 1 1 Setting invalid -
IM3-1,
IM0
I 4
VSSD/
IOVcc
Note:
If the serial data transfer interface was selected, IM0 pin is used
like the ID setting for the device code in transfer data.
NCS I 1 MPU
Chip select signal.
Low: chip can be accessed;
High: chip cannot be accessed. Must be connected to VSSD if
not in use.
VLD I 1 MPU Fix to VSSD
RS I 1 MPU
The signal for register index or register command select.
Low: Register index or internal status (in read operation);
High: Register command.
Connect to IOVcc or VSSD level when serial data transfer
interface is selected.
E_NWR I 1 MPU
Serves as a write signal and writes data at the rising edge in i80
system interface.
Serves as the synchronous clock signal in serial data transfer
interface.
RW_NRD I 1 MPU
Low: Write；High: Read)
Serves as a read signal and reads data at the low level in i80
system interface. Fix it to IOVcc or VSSD level when using
serial data transfer interface.
ENABLE I 1 MPU
A data ENABLE signal in RGB I/F mode. Fix the unused pin to
either the VSSD level or the IOVcc level.
Low: Selected (access enabled)
The polarity of the ENABLE signal is inverted by the EPL bit.
EPL ENABLE RAM write RAM address
0 0 Enable Update
0 1 Disable Keep
1 0 Disable Keep
1 1 Enable Update
VSYNC I 1 MPU
Frame synchronizing signal. Fix to the IOVcc level when not
used.
If VSPL=0: Active low.
If VSPL=1: Active high.
HSYNC I 1 MPU
Frame synchronizing signal. Fix to the IOVcc level when not
used.
If HSPL=0: Active low.
If HSPL=1: Active high.
DOTCLK I 1 MPU
Dot clock signal. Fix to the IOVcc level when not used.
If DPL=0: Data are input on the rising edge of DOTCLK.
If DPL=1: Data are input on the falling edge of DOTCLK.
PD0~17 I 18 MPU
An 18-bit bus RGB data bus in 80-system interface mode. Fix
the unused pins to either the VSSD level or the IOVcc level.
6-bit bus: use PD17-PD12
16-bit bus: use PD17-PD13 and PD11-PD1
