Cavium Networks Confidential
Page 1
OCTEON
Technical Presentation
Cavium Networks Confidential
Page 2
Agenda
●
Lesson One
Octeon Architecture Introduce
Octeon 报文处理流程
●
Lesson Two
FPA
Timer
●
Lesson Three
PIP/IPD
PKO
●
Lesson Four
SSO
●
Lesson Five
Software overview
Cavium Networks Confidential
Page 3
3
OCTEON 多核处理器
架构介绍
Cavium Networks Confidential
Page 4
2MB Shared
L2 Cache
Hyper
Access
Memory
Controller
Hyper
Access
Memory
Controller
Coherent,
Low-latency
Interconnect
Hyper Access Low Latency
Memory Controller
Hyper Access Low Latency
Memory Controller
Optional 2x18-bit
RLDRAM2
DDR2 up to
800 MHz
72 or 144-bit wide
SPI 4.2
or
4x RGMII
SPI 4.2
or
4x RGMII
Boot/flash
GPIO
2xUART
64-bit,
133MHz
Compress
/ Decomp
Compress
/ Decomp
32x RegEx
Engines
32x RegEx
Engines
Packet
Interface
Packet
Interface
Packet
Interface
Packet
Interface
Misc I/O
Misc I/O
Secure
Vault
Secure
Vault
PCI-X
PCI-X
TCP Unit
TCP Unit
I
/
O
B
u
s
Sched/
Synch/
Order
Sched/
Synch/
Order
Up to
16
cnMIPS
+
cores
Security
MIPS64 r2
Integer
Packet
32K Icache
16K Dcache
2K Write
Buffer
Security
MIPS64 r2
Integer
Packet
32K Icache
16K Dcache
2K Write
Buffer
Packet
Input
Packet
Input
Packet
Output
Packet
Output
I/O
Bridge
I/O
Bridge
640 Gbps
1
3
6
G
b
p
s
OCTEON Plus CN58XX
Cavium Networks Confidential
Page 5
Low-latency
Interconnect
DDR2-800
1x or 2x 72bit wide
(with ECC)
Boot/flash,
GPIO, MISC,
USB2.0, FE
I
/
O
B
u
s
Sched/
Synch/
Order
Sched/
Synch/
Order
8 - 12
cnMIPS
+
Cores
Security
MIPS64 r2
Integer
Packet
32K Icache
16K Dcache
2K Write
Buffer
Packet
Input
Packet
Input
I/O
Bridge
I/O
Bridge
2MB
L2 Cache
Hyper Access
Memory
Controller
Security
MIPS64 r2
Integer
Packet
32K Icache
16K Dcache
2K Write
Buffer
Packet
Output
Packet
Output
TCP Unit
TCP Unit
Compression +
Decompression
Compression +
Decompression
4
x
PCIe
Core
PCIe
Core
4x SGMII or
4x 1000B-X
or XAUI
4
x
4
x
4
x
S
w
i
t
c
h
P
C
I
e
E
n
g
i
n
e
s
4x SGMII or
4x 1000B-X
or XAUI
Other I/O
Other I/O
x16 Serdes
enables
combination of
PCIe (2
controllers),
XAUI, SGMII and
up to double
speed PICMG
interfaces with
PCIe switching *
DMA
Engines
DMA
Engines
* Interface Options
* Interface Options
●
8-lanes PCIe + 8-lanes PCIe
8-lanes PCIe + 8-lanes PCIe
●
8-lanes PCIe + 4-lanes PCIe + [4x SGMII or XAUI]
8-lanes PCIe + 4-lanes PCIe + [4x SGMII or XAUI]
●
2x [4-lanes PCIe] + 2x [4x SGMII or XAUI]
2x [4-lanes PCIe] + 2x [4x SGMII or XAUI]
RAID
RAID
OCTEON Plus CN56/57XX
