fpga分频程序

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY div50m IS PORT(clk: IN STD_LOGIC; co: OUT STD_LOGIC); END div50m; ARCHITECTURE fun OF div50m IS SIGNAL q:INTEGER range 0 to 50000000-1; BEGIN PROCESS(clk) BEGIN IF(clk'EVENT AND clk='1') THEN IF q=50000000-1 THEN q<=0; co<='1'; ELSE q<=q+1; co<='0'; END IF; END IF; END PROCESS; END fun;