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Altera Device Package Information

Data Sheet

This data sheet provides package and thermal resistance information for

Altera

devices. Package information includes the ordering code reference, package

acronym, leadframe material, lead finish (plating), JEDEC outline reference, lead

coplanarity, weight, moisture sensitivity level, and other special information. The

thermal resistance information includes device pin count, package name, and

resistance values.

This data sheet includes the following sections:

■ “Device and Package Cross Reference” (below)

■ “Thermal Resistance” on page 31

■ “Package Outlines” on page 62

f For information about trays, tubes, and dry packs, refer to AN 71: Guidelines for

Handling J-Lead, QFP, and BGA Devices.

Device and Package Cross Reference

Tabl e 2 through Tab le 37 lists the device, package type, and number of pins for each

Altera device. Altera devices are available in the following packages:

■ Ball-Grid Array (BGA)

■ FineLine BGA (FBGA)

■ Hybrid FineLine BGA (HBGA)

■ Micro FineLine BGA (MBGA)

■ Ultra FineLine BGA (UBGA)

■ Ceramic Pin-Grid Array (PGA)

■ Ceramic Dual In-Line Package (CerDIP)

■ Plastic J-Lead Chip Carrier (PLCC)

■ Plastic Enahnced Quad Flat Pack (EQFP)

■ Plastic Quad Flat Pack (PQFP)

■ Thin Quad Flat Pack (TQFP)

■ Plastic Dual In-Line Package (PDIP)

■ Power Quad Flat Pack (RQFP)

■ Small outline Circuit Package (SOIC)

■ Quad Flat No-Lead Package (QFN)

DS-PKG-16.1

Device and Package Cross Reference

Altera Device Package Information Data Sheet © April 2010 Altera Corporation

Tabl e 1 lists the Altera devices and the associated table locations.

Table 1. Altera Device and Package Cross Reference

Altera Device Table locations

Arria

series FPGAs

■ Arria II GX Devices: Table 2 on page 3

■ Arria GX Devices: Table 3 on page 3

Stratix

series FPGAs

■ Stratix IV Devices: Table 4 on page 4

■ Stratix III Devices: Table 5 on page 6

■ Stratix II Devices: Table 6 on page 7

■ Stratix II GX Devices: Table 7 on page 8

■ Stratix GX Devices: Table 8 on page 8

■ Stratix Devices: Table 9 on page 9

Cyclone

series FPGAs

■ Cyclone IV Devices: Table 10 on page 10

■ Cyclone IV GX Devices: Table 11 on page 11

■ Cyclone III LS Devices: Table 12 on page 12

■ Cyclone III Devices: Table 13 on page 12

■ Cyclone II Devices: Table 14 on page 14

■ Cyclone Devices: Table 15 on page 15

MAX

series CPLDs

■ MAX II Devicess: Table 16 on page 15

■ MAX 9000 Devices: Table 17 on page 16

■ MAX 7000B Devices: Table 18 on page 16

■ MAX 7000AE Devices: Table 19 on page 17

■ MAX 7000A Devices: Table 20 on page 18

HardCopy

series ASICs

■ HardCopy IV E Devices: Table 21 on page 18

■ HardCopy IV GX Devices: Table 22 on page 19

■ HardCopy III Devices: Table 23 on page 20

■ HardCopy II Devices: Table 24 on page 20

■ HardCopy Devices: Table 25 on page 21

■ HardCopy APEX Devices: Table 26 on page 21

APEX™ series FPGAs

■ APEX II Devices: Table 27 on page 21

■ APEX 20K E Devices: Table 28 on page 22

■ APEX 20K C Devices: Table 29 on page 23

■ APEX 20K Devices: Table 30 on page 24

ACEX

1K FPGAs ACEX 1K Devices: Table 31 on page 25

Mercury™ FPGAs Mercury Devices: Table 32 on page 25

FLEX

series FPGAs

■ FLEX 10KA Devices: Table 33 on page 26

■ FLEX 10KS Devices: Table 34 on page 27

■ FLEX 10KE Devices: Table 35 on page 27

Excalibur™ FPGAs Excalibur Devices: Table 36 on page 29

Enhanced configuration devices Enhanced Configuration Devices: Table 37 on page 30

Device and Package Cross Reference

Altera Device Package Information Data Sheet © April 2010 Altera Corporation

Stratix IV Devices

Tabl e 4 lists the device name, package type, and number of pins for the Stratix IV

device family.

1 The package type entries with “Option #” refer to instances where multiple package

options exist for a given package type and pin count. The option number identifies the

specific type used by the corresponding device density.

EP1AGX50