linux内核驱动详解2

/* * Intel i810 and friends ICH driver for Linux * Alan Cox <alan@redhat.com> * * Built from: * Low level code: Zach Brown (original nonworking i810 OSS driver) * Jaroslav Kysela <perex@suse.cz> (working ALSA driver) * * Framework: Thomas Sailer <sailer@ife.ee.ethz.ch> * Extended by: Zach Brown <zab@redhat.com> * and others.. * * Hardware Provided By: * Analog Devices (A major AC97 codec maker) * Intel Corp (you've probably heard of them already) * * AC97 clues and assistance provided by * Analog Devices * Zach 'Fufu' Brown * Jeff Garzik * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. * * * Intel 810 theory of operation * * The chipset provides three DMA channels that talk to an AC97 * CODEC (AC97 is a digital/analog mixer standard). At its simplest * you get 48Khz audio with basic volume and mixer controls. At the * best you get rate adaption in the codec. We set the card up so * that we never take completion interrupts but instead keep the card * chasing its tail around a ring buffer. This is needed for mmap * mode audio and happens to work rather well for non-mmap modes too. * * The board has one output channel for PCM audio (supported) and * a stereo line in and mono microphone input. Again these are normally * locked to 48Khz only. Right now recording is not finished. * * There is no midi support, no synth support. Use timidity. To get * esd working you need to use esd -r 48000 as it won't probe 48KHz * by default. mpg123 can't handle 48Khz only audio so use xmms. * * Fix The Sound On Dell * * Not everyone uses 48KHz. We know of no way to detect this reliably * and certainly not to get the right data. If your i810 audio sounds * stupid you may need to investigate other speeds. According to Analog * they tend to use a 14.318MHz clock which gives you a base rate of * 41194Hz. * * This is available via the 'ftsodell=1' option. * * If you need to force a specific rate set the clocking= option * * This driver is cursed. (Ben LaHaise) * * ICH 3 caveats * Intel errata #7 for ICH3 IO. We need to disable SMI stuff * when codec probing. [Not Yet Done] * * ICH 4 caveats * * The ICH4 has the feature, that the codec ID doesn't have to be * congruent with the IO connection. * * Therefore, from driver version 0.23 on, there is a "codec ID" <-> * "IO register base offset" mapping (card->ac97_id_map) field. * * Juergen "George" Sawinski (jsaw) */ #include <linux/module.h> #include <linux/string.h> #include <linux/ctype.h> #include <linux/ioport.h> #include <linux/sched.h> #include <linux/delay.h> #include <linux/sound.h> #include <linux/slab.h> #include <linux/soundcard.h> #include <linux/pci.h> #include <linux/interrupt.h> #include <asm/io.h> #include <asm/dma.h> #include <linux/init.h> #include <linux/poll.h> #include <linux/spinlock.h> #include <linux/smp_lock.h> #include <linux/ac97_codec.h> #include <linux/bitops.h> #include <asm/uaccess.h> #define DRIVER_VERSION "1.01" #define MODULOP2(a, b) ((a) & ((b) - 1)) #define MASKP2(a, b) ((a) & ~((b) - 1)) static int ftsodell; static int strict_clocking; static unsigned int clocking; static int spdif_locked; static int ac97_quirk = AC97_TUNE_DEFAULT; //#define DEBUG //#define DEBUG2 //#define DEBUG_INTERRUPTS //#define DEBUG_MMAP //#define DEBUG_MMIO #define ADC_RUNNING 1 #define DAC_RUNNING 2 #define I810_FMT_16BIT 1 #define I810_FMT_STEREO 2 #define I810_FMT_MASK 3 #define SPDIF_ON 0x0004 #define SURR_ON 0x0010 #define CENTER_LFE_ON 0x0020 #define VOL_MUTED 0x8000 /* the 810's array of pointers to data buffers */ struct sg_item { #define BUSADDR_MASK 0xFFFFFFFE u32 busaddr; #define CON_IOC 0x80000000 /* interrupt on completion */ #define CON_BUFPAD 0x40000000 /* pad underrun with last sample, else 0 */ #define CON_BUFLEN_MASK 0x0000ffff /* buffer length in samples */ u32 control; }; /* an instance of the i810 channel */ #define SG_LEN 32 struct i810_channel { /* these sg guys should probably be allocated separately as nocache. Must be 8 byte aligned */ struct sg_item sg[SG_LEN]; /* 32*8 */ u32 offset; /* 4 */ u32 port; /* 4 */ u32 used; u32 num; }; /* * we have 3 separate dma engines. pcm in, pcm out, and mic. * each dma engine has controlling registers. These goofy * names are from the datasheet, but make it easy to write * code while leafing through it. * * ICH4 has 6 dma engines, pcm in, pcm out, mic, pcm in 2, * mic in 2, s/pdif. Of special interest is the fact that * the upper 3 DMA engines on the ICH4 *must* be accessed * via mmio access instead of pio access. */ #define ENUM_ENGINE(PRE,DIG) \ enum { \ PRE##_BASE = 0x##DIG##0, /* Base Address */ \ PRE##_BDBAR = 0x##DIG##0, /* Buffer Descriptor list Base Address */ \ PRE##_CIV = 0x##DIG##4, /* Current Index Value */ \ PRE##_LVI = 0x##DIG##5, /* Last Valid Index */ \ PRE##_SR = 0x##DIG##6, /* Status Register */ \ PRE##_PICB = 0x##DIG##8, /* Position In Current Buffer */ \ PRE##_PIV = 0x##DIG##a, /* Prefetched Index Value */ \ PRE##_CR = 0x##DIG##b /* Control Register */ \ } ENUM_ENGINE(OFF,0); /* Offsets */ ENUM_ENGINE(PI,0); /* PCM In */ ENUM_ENGINE(PO,1); /* PCM Out */ ENUM_ENGINE(MC,2); /* Mic In */ enum { GLOB_CNT = 0x2c, /* Global Control */ GLOB_STA = 0x30, /* Global Status */ CAS = 0x34 /* Codec Write Semaphore Register */ }; ENUM_ENGINE(MC2,4); /* Mic In 2 */ ENUM_ENGINE(PI2,5); /* PCM In 2 */ ENUM_ENGINE(SP,6); /* S/PDIF */ enum { SDM = 0x80 /* SDATA_IN Map Register */ }; /* interrupts for a dma engine */ #define DMA_INT_FIFO (1<<4) /* fifo under/over flow */ #define DMA_INT_COMPLETE (1<<3) /* buffer read/write complete and ioc set */ #define DMA_INT_LVI (1<<2) /* last valid done */ #define DMA_INT_CELV (1<<1) /* last valid is current */ #define DMA_INT_DCH (1) /* DMA Controller Halted (happens on LVI interrupts) */ #define DMA_INT_MASK (DMA_INT_FIFO|DMA_INT_COMPLETE|DMA_INT_LVI) /* interrupts for the whole chip */ #define INT_SEC (1<<11) #define INT_PRI (1<<10) #define INT_MC (1<<7) #define INT_PO (1<<6) #define INT_PI (1<<5) #define INT_MO (1<<2) #define INT_NI (1<<1) #define INT_GPI (1<<0) #define INT_MASK (INT_SEC|INT_PRI|INT_MC|INT_PO|INT_PI|INT_MO|INT_NI|INT_GPI) /* magic numbers to protect our data structures */ #define I810_CARD_MAGIC 0x5072696E /* "Prin" */ #define I810_STATE_MAGIC 0x63657373 /* "cess" */ #define I810_DMA_MASK 0xffffffff /* DMA buffer mask for pci_alloc_consist */ #define NR_HW_CH 3 /* maxinum number of AC97 codecs connected, AC97 2.0 defined 4 */ #define NR_AC97 4 /* Please note that an 8bit mono stream is not valid on this card, you must have a 16bit */ /* stream at a minimum for this card to be happy */ static const unsigned sample_size[] = { 1, 2, 2, 4 }; /* Samples are 16bit values, so we are shifting to a word, not to a byte, hence shift */ /* values are one less than might be expected */ static const unsigned sample_shift[] = { -1, 0, 0, 1 }; enum { ICH82801AA = 0, ICH82901AB, INTEL440MX, INTELICH2, INTELICH3, INTELICH4, INTELICH5, SI7012, NVIDIA_NFORCE, AMD768, AMD8111 }; static char * card_names[] = { "Intel ICH 82801AA", "Intel ICH 82901AB", "Intel 440MX", "Intel ICH2", "I