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### 关于DSP芯片资料的关键知识点 #### 一、概述本文档主要介绍了一款名为AD14060/AD14060L的Quad-SHARC DSP多处理器家族的相关技术细节。这款芯片由Analog Devices公司设计制造，旨在为高性能数字信号处理应用提供强大的计算能力和灵活性。 #### 二、性能特点 1. **ADSP-21060 Core Processor** - 每个处理器具有25纳秒的指令周期时间，单周期指令执行能力。 - 四个处理器协同工作时，峰值性能可达480 MFLOPS（每秒百万次浮点运算），持续性能为320 MFLOPS。 2. **内存管理** - 配备16 Mbit的内部共享SRAM（静态随机存取存储器）。 - 支持高达4 Gigawords的外部模块内存地址空间，满足大量数据处理的需求。 3. **通信接口** - 包含十二个40 Mbyte/s的链接端口，每个SHARC拥有三个这样的端口。 - 提供四个独立的40 Mbit/s串行端口，每个SHARC配备一个。 - 另有一个公共的40 Mbit/s串行端口。 4. **电源与数据格式** - 支持5 V和3.3 V操作电压。 - 数据格式支持32位单精度浮点和40位扩展精度浮点，也可选择32位定点数据格式。 - 遵循IEEE JTAG标准1149.1，提供测试访问端口和片上仿真功能。 #### 三、封装特性 1. **物理规格** - 采用308引脚陶瓷四方扁平封装（CQFP）。 - 封装尺寸为2.05英寸（52毫米）。 - 支持腔体向上或向下配置。 - 具有低剖面，高度仅0.160英寸。 - 封装为气密性。 2. **热性能** - 典型重量为29克。 - 热阻（uJC）为0.368 C/W。 #### 四、一般描述 1. **产品定位** - AD14060/AD14060L是SHARC系列中的首款高性能DSP多处理器模块。 - 在其同类产品中拥有最高的性能密度和最低的成本效益比。 2. **核心组件** - 基于ADSP-21060 DSP微计算机构建，利用了其内置的多处理特性。 - 通过单一芯片类型实现了480 MFLOPS的峰值性能。 3. **内存扩展** - DSP芯片内部的SRAM提供了16 Mbits的共享内存资源。 - 完整的共享总线（48位数据，32位地址）也被引出模块外，用于扩展内存或其他外围设备的连接。 4. **应用场景** - 适用于那些需要高单位面积性能和/或功能的应用场景。 - 特别适合于高性能数字信号处理系统，如高级音频处理、图像识别、雷达信号处理等领域。 #### 五、结论 AD14060/AD14060L Quad-SHARC是一款高度集成且性能卓越的DSP多处理器模块。它不仅提供了强大的计算能力，还具备灵活的内存管理和丰富的通信接口选项，非常适合应用于需要高性能处理能力的场合。此外，其紧凑的封装形式和良好的热性能也为实际应用带来了极大的便利。

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REV. A

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

AD14060/AD14060L

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700 World Wide Web Site: http://www.analog.com

Fax: 781/326-8703 © Analog Devices, Inc., 1997

Quad-SHARC

DSP Multiprocessor Family

FUNCTIONAL BLOCK DIAGRAM

PERFORMANCE FEATURES

ADSP-21060 Core Processor (

...

34)

480 MFLOPS Peak, 320 MFLOPS Sustained

25 ns Instruction Rate, Single-Cycle

Instruction Execution–Each of Four Processors

16 Mbit Shared SRAM (Internal to SHARCs)

4 Gigawords Addressable Off-Module Memory

Twelve 40 Mbyte/s Link Ports (Three per SHARC)

Four 40 Mbit/s Independent Serial Ports (One from

Each SHARC)

One 40 Mbit/s Common Serial Port

5 V and 3.3 V Operation

32-Bit Single Precision and 40-Bit Extended

Precision IEEE Floating Point Data Formats, or

32-Bit Fixed Point Data Format

IEEE JTAG Standard 1149.1 Test Access Port and

On-Chip Emulation

PACKAGING FEATURES

308-Lead Ceramic Quad Flatpack (CQFP)

2.05" (52 mm) Body Size

Cavity Up or Down, Configurable

Low Profile, 0.160" Height

Hermetic

25 Mil (0.65 mm) Lead Pitch

29 Grams (typical)

= 0.368C/W

GENERAL DESCRIPTION

The AD14060/AD14060L Quad-SHARC is the first in a family

of high performance DSP multiprocessor modules. The core of

the multiprocessor is the ADSP-21060 DSP microcomputer.

The AD14060/AD14060L modules have the highest perfor-

mance —density and lowest cost—performance ratios of any in

their class. They are ideal for applications requiring higher levels

of performance and/or functionality per unit area.

The AD14060/AD14060L takes advantage of the built-in multi-

processing features of the ADSP-21060 to achieve 480 peak

MFLOPS with a single chip type, in a single package. The on-

chip SRAM of the DSPs provides 16 Mbits of on-module

shared SRAM. The complete shared bus (48 data, 32 address)

is also brought off-module for interfacing with expansion

memory or other peripherals.

SHARC is a registered trademark of Analog Devices, Inc.

The ADSP-21060 link ports are interconnected to provide

direct communication among the four SHARCs as well as high

speed off-module access. Internally, each SHARC has a direct

link port connection. Externally, each SHARC has a total of

120 Mbytes/s link port bandwidth.

Multiprocessor performance is enhanced with embedded power

and ground planes, matched impedance interconnect, and opti-

mized signal routing lengths and separation. The fully tested

and ready-to-insert multiprocessor also significantly reduces

board space.

CPA

SPORT 1

TDI

EBOOT,

LBOOT, BMS

TIMEXP

LINK 1

LINK 3

LINK 4

IRQ

2-0

FLAG

2,0

EMU

CLKIN

RESET

SPORT 0

TCK, TMS, TRST

FLAG

SHARC_A

(ID

2-0

= 1)

CPA

SPORT 1

EBOOT,

LBOOT, BMS

TIMEXP

LINK 1

LINK 3

LINK 4

IRQ

2-0

FLAG

2,0

EMU

CLKIN

RESET

SPORT 0

TCK, TMS, TRST

FLAG

TDO

SHARC_B

(ID

2-0

= 2)

LINK 0

LINK 2

LINK 5

TDI

LINK 0

LINK 2

LINK 5

TDO

EBOOT,

LBOOT, BMS

EMU

CLKIN

RESET

SPORT 0

TCK, TMS, TRST

FLAG

LINK 0

LINK 2

LINK 5

TDO

LINK 0

LINK 2

LINK 5

TDI

EBOOT,

LBOOT, BMS

EMU

CLKIN

RESET

SPORT 0

TCK, TMS, TRST

FLAG

TDI

SHARC BUS (

ADDR

31-0

DATA

47-0,

3-0

RD, WR, PAGE, ADRCLK, SW, ACK,

SBTS, HBR, HBG, REDY, BR

6-1

, RPBA, DMAR

1.2

, DMAG

1.2

)

CPA

SPORT 1

TDO

TIMEXP

LINK 1

LINK 3

LINK 4

IRQ

2-0

FLAG

2,0

CPA

SPORT 1

SHARC_D

(ID

2-0

= 4)

SHARC_C

(ID

2-0

= 3)

TIMEXP

LINK 1

LINK 3

LINK 4

IRQ

2-0

FLAG

2,0

AD14060/

AD14060L

AD14060/AD14060L

–2–

REV. A

DETAILED DESCRIPTION

Architectural Features

ADSP-21060 Core

The AD14060/AD14060L is based on the powerful ADSP-21060

(SHARC) DSP chip. The ADSP-21060 SHARC combines a

high performance floating-point DSP core with integrated, on-

chip system features including a 4 Mbit SRAM memory, host

processor interface, DMA controller, serial ports, and both link

port and parallel bus connectivity for glueless DSP multiprocess-

ing, (see Figure 1). It is fabricated in a high speed, low power

CMOS process, and has a 25 ns instruction cycle time. The arith-

metic/ logic unit (ALU), multiplier and shifter all perform single-

cycle instructions, and the three units are arranged in parallel,

maximizing computational throughput.

The SHARC features an enhanced Harvard architecture in

which the data memory (DM) bus transfers data, and the pro-

gram memory (PM) bus transfers both instructions and data.

There is also an on-chip instruction cache which selectively

caches only those instructions whose fetches conflict with the

PM bus data accesses. This combines with the separate program

and data memory buses to enable three-bus operation for fetch-

ing an instruction and two operands, all in a single cycle. The

SHARC also contains a general purpose data register file, which

is a 10-port, 32-register (16 primary, 16 secondary) file. Each

SHARC’s core also implements two data address generators

(DAGs), implementing circular data buffers in hardware. The

DAGs contain sufficient registers to allow the creation of up to

32 circular buffers. The 48-bit instruction word accommodates a

variety of parallel operations, for concise programming. For ex-

ample, the ADSP-21060 can conditionally execute a multiply, an

add, a subtract, and a branch, all in a single instruction.

The SHARCs contain 4 Mbits of on-chip SRAM each, orga-

nized as two blocks of 2 Mbits, which can be configured for

different combinations of code and data storage. The memory

can be configured as a maximum of 128K words of 32-bit data,

256K words of 16-bit data, 80K words of 48-bit instructions (or

40-bit data), or combinations of different word sizes up to

4 megabits. A 16-bit floating-point storage format is supported

which effectively doubles the amount of data that may be stored

on chip. Conversion between the 32-bit floating point and 16-

bit floating point formats is done in a single instruction. Each

memory block is dual-ported for single-cycle, independent

accesses by the core processor and I/O processor or DMA con-

troller. The dual-ported memory and separate on-chip buses

allow two data transfers from the core and one from I/O, all in a

single cycle.

Shared Memory Multiprocessing

The AD14060/AD14060L takes advantage of the powerful

multiprocessing features built into the SHARC. The SHARCs are

connected to maximize the performance of this cluster-of-four

architecture, and still allow for off-module expansion. The

AD14060/AD14060L in itself is a complete shared memory

multiprocessing system, as shown in Figure 3. The unified ad-

dress space of the SHARCs allows direct interprocessor ac-

cesses of each SHARCs’ internal memory. In other words, each

SHARC can directly access the internal memory and IOP registers

of each of the other SHARCs by simply reading or writing to the

appropriate address in multiprocessor memory space (see Figure

2)—this is called a direct read or direct write.

SERIAL PORTS

(2)

LINK PORTS

(6)

IOP

REGISTERS

(

MEMORY MAPPED)

CONTROL,

STATUS, AND

DATA BUFFERS

I/O PROCESSOR

TIMER

INSTRUCTION

CACHE

32 x 48-BIT

ADDR DATA

DATA

ADDR

ADDR DATA ADDR

TWO INDEPENDENT

DUAL-PORTED BLOCKS

PROCESSOR PORT I/O PORT

BLOCK 0

BLOCK 1

JTAG

TEST AND

EMULATION

HOST PORT

ADDR BUS

MUX

IOA

IOD

MULTIPROCESSOR

INTERFACE

DUAL-PORTED SRAM

EXTERNAL

PORT

DATA BUS

MUX

24PM ADDRESS BUS

DM ADDRESS BUS

PM DATA BUS

DM DATA BUS

BUS

CONNECT

(PX)

DATA

FILE

16 x 40-BIT

BARREL

SHIFTER

ALUMULTIPLIER

DAG1

8 x 4 x 32

40/32

CORE PROCESSOR

DMA

CONTROLLER

PROGRAM

SEQUENCER

DAG2

8 x 4 x 24

Figure 1. ADSP-21060 Processor Block Diagram (Core of the AD14060)

AD14060/AD14060L

–4–

REV. A

Bus arbitration is accomplished with the on-SHARC arbitration

logic. Each SHARC has a unique ID, and drives the Bus-Request

(BR) line corresponding to its ID, while monitoring all others.

BR1–BR4 are used within the AD14060/AD14060L, while BR5

and BR6 can be used for expansion. All bus requests (BR1–BR6)

are included in the module I/O.

Two different priority schemes, fixed and rotating, are available

to resolve competing bus requests. The RPBA pin selects which

scheme is used: when RPBA is high, rotating priority bus arbitra-

tion is selected, and when RPBA is low, fixed priority is selected.

Table I. Rotating Priority Arbitration Example

Hardware Processor IDs

Cycle ID1 ID2 ID3 ID4 ID5 ID6

1M12 BR345Initial Priority Assignments

2 4 5 BR M-BR 1 2 3

3 4 5 BR M 1 2 3

4 5 BR M 1 2 3 4 BR

51 BR2345MFinal Priority Assignments

NOTES

1–5 = Assigned Priority.

M = Bus Mastership (in that cycle).

BR = Requesting Bus Mastership with BRx.

Bus mastership is passed from one SHARC to another during a

bus transition cycle. A bus transition cycle only occurs when the

current bus master deasserts its BR line and one of the slave

SHARCs asserts its BR line. The bus master can therefore re-

tain bus mastership by keeping its BR line asserted. When the

bus master deasserts its BR line, and no other BR line is as-

serted, then the master will not lose any bus cycles. When more

than one SHARC asserts its BR line, the SHARC with the

highest priority request becomes bus master on the following

cycle. Each SHARC observes all of the BR lines, and therefore

tracks when a bus transition cycle has occurred, and which

processor has become the new bus master. Master processor

changeover incurs only one cycle of overhead. An example bus

transition sequence is shown in Table I.

Bus locking is possible, allowing indivisible read-modify-write

sequences for semaphores. In either the fixed or rotating priority

scheme, it is also possible to limit the number of cycles the

master can control the bus. The AD14060/AD14060L also

provides the option of using the Core Priority Access (CPA)

mode of the SHARC. Using the CPA signal allows external bus

accesses by the core processor of a slave SHARC to take priority

over ongoing DMA transfers. Also, each SHARC can broadcast

write to all other SHARCs simultaneously, allowing the imple-

mentation of reflective semaphores.

The bus master can communicate with slave SHARCs by writ-

ing messages to their internal IOP registers. The MSRG0–

MSRG7 registers are general-purpose registers that can be used

for convenient message passing, semaphores and resource shar-

ing between the SHARCs. For message passing, the master

communicates with a slave by writing and/or reading any of the

eight message registers on the slave. For vector interrupts, the

master can issue a vector interrupt to a slave by writing the

address of an interrupt service routine to the slave’s VIRPT

slave which, when serviced, will cause it to branch to the speci-

fied service routine.

Off-Module Memory and Peripherals Interface

The AD14060/AD14060L’s external port provides the interface to

off-module memory and peripherals (see Figure 5). This port

consists of the complete external port bus of the SHARC, bused

together in common among the four SHARCs.

The 4-gigaword off-module address space is included in the

ADSP-14060’s unified address space. Addressing of external

memory devices is facilitated by each SHARC internally de-

coding the high order address lines to generate memory bank

select signals. Separate control lines are also generated for sim-

plified addressing of page-mode DRAM. The AD14060/

AD14060L also supports programmable memory wait states and

external memory acknowledge controls to allow interfacing to

DRAM and peripherals with variable access, hold and disable

time requirements.

Link Port I/O

Each individual SHARC features six 4-bit link ports that facili-

tate SHARC-to-SHARC communication and external I/O inter-

facing. Each link port can be configured for either 1× or 2×

operation, allowing each to transfer either 4 or 8 bits per cycle.

The link ports can operate independently and simultaneously,

with a maximum bandwidth of 40 MBytes/s each, or a total of

240 MBytes/s per SHARC.

The AD14060/AD14060L optimizes the link port connections

internally, and brings a total of twelve of the link ports off-mod-

ule for user-defined system connections. Internally, each SHARC

has a connection to the other three SHARCs with a dedicated

link port interface. Thus, each SHARC can directly interface

with its nearest and next-nearest neighbor. The remaining three

link ports from each SHARC are brought out independently

from each SHARC. A maximum of 480 MBytes/s link port

bandwidth is then available off of the AD14060/AD14060L.

The link port connections are detailed in Figure 4.

SHARC_A SHARC_B

SHARC_D SHARC_C

Figure 4. Link Port Connections

Link port 4, the boot link port, is brought off independently

from each SHARC. Individual booting is then allowed, or

chained link port booting is possible as described under “Link

Port Booting.”

Link port data is packed into 32-bit or 48-bit words, and can

be directly read by the SHARC core processor or DMA-

transferred to on-SHARC memory.

Each link port has its own double-buffered input and output

registers. Clock/acknowledge handshaking controls link port

transfers. Transfers are programmable as either transmit or

receive.

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