Table of Contents
COVER ………………………………………………………………………………………………………………………………………………………………………..1
PRODUCT OVERVIEW .......................................................................................................................................................... 3
DOCUMENT PURPOSE ............................................................................................................................................................. 14
NUMBER REPRESENTATION ...................................................................................................................................................... 14
NAMING CONVENTIONS .......................................................................................................................................................... 14
1 INTRODUCTION ........................................................................................................................................... 16
1.1
SOC DEVICE FEATURES ...................................................................................................................................... 16
2 FUNCTIONAL DESCRIPTION OVERVIEW........................................................................................................ 19
2.1
ARCHITECTURE OVERVIEW ................................................................................................................................ 19
2.2
CHIP CONFIGURATION ........................................................................................................................................ 20
2.3
MEMORY MAP .................................................................................................................................................... 20
2.4
DMA CONNECTIVITY AND ASSIGNMENTS .......................................................................................................... 23
3 PIN MUXING AND MULTI-FUNCTION PINS ................................................................................................... 27
3.1
FUNCTION ASSIGNMENTS FOR MULTIPLEXED I/O PINS .................................................................................................... 27
3.2
PINOUT ................................................................................................................................................................. 30
3.3
MULTIPLEXED SIGNAL FUNCTIONS .............................................................................................................................. 42
3.4
PAD-RING I/O DOMAINS POWER CONTROL .................................................................................................................. 46
3.5
PIN CONTROL UNIT ................................................................................................................................................. 51
3.6
FUNCTION ASSIGNMENTS FOR MULTI-FUNCTION I/O PINS.............................................................................................. 63
3.7
REGISTER DESCRIPTIONS ........................................................................................................................................... 68
4 ARM CORTEX-A7 .......................................................................................................................................... 69
4.1
CA7 OVERVIEW ...................................................................................................................................................... 69
4.2
CA7 FUNCTIONAL DESCRIPTION ................................................................................................................................ 70
4.3
CA7 INTERRUPT ................................................................................................................................................. 74
5 XM6 ............................................................................................................................................................. 80
5.1
OVERVIEW .......................................................................................................................................................... 80
5.2
PROGRAM GUIDE ................................................................................................................................................ 84
6 DDR MEMORY CONTROLLER ........................................................................................................................ 88
6.1 INTRODUCTION ................................................................................................................................................... 88
6.2 FEATURE LIST ..................................................................................................................................................... 88
6.3 OVERVIEW .......................................................................................................................................................... 90
6.4 FUNCTIONAL DESCRIPTION ................................................................................................................................. 91
7 SD HOST CONTROLLER ............................................................................................................................... 101
7.1
FEATURES ............................................................................................................................................................ 101
7.2
SIGNAL DESCRIPTIONS ............................................................................................................................................ 103
7.3
SD/MMC BUS PROTOCOL DESCRIPTION .................................................................................................................. 103
7.4
SPECIAL BUS TRANSACTIONS ................................................................................................................................... 105
7.5
SEQUENCES OF HOST AND CARD INTERACTION ............................................................................................................ 107
7.6
CARD DETECTION .................................................................................................................................................. 112
7.7
SPI MODE ........................................................................................................................................................... 112
7.8
MMC MODE ....................................................................................................................................................... 112
7.9
CE-ATA MODE .................................................................................................................................................... 112
7.10
REGISTER DESCRIPTIONS ......................................................................................................................................... 112
8 POWER MANAGEMENT AND CLOCKS ........................................................................................................ 113
8.1 POWER MANAGEMENT UNITS ................................................................................................................................. 113
