Intel64&32技术手册：卷IIA指令集A-M资源-CSDN文库

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NOTE: The Intel® 64 and IA-32 Architectures Software Developer's Manual consists of five volumes: Basic Architecture, Order Number 253665; Instruction Set Reference A-M, Order Number 253666; Instruction Set Reference N-Z, Order Number 253667; System Programming Guide, Part 1, Order Number 253668; System Programming Guide, Part 2, Order Number 253669. Refer to all five volumes when evaluating your design needs. 根据给定文件信息，我们可以提取出以下知识点： 1. Intel® 64和IA-32架构的软件开发手册由五个部分组成：基础架构、指令集参考A-M、指令集参考N-Z、系统编程指南第1部分和系统编程指南第2部分。每部分都有相应的订单号码，分别为253665、253666、253667、253668和253669。在评估设计需求时应参考所有五卷。 2. 指令集参考A-M部分的订单号码为253666-035US，发布于2010年6月。这份文档提供了与Intel产品相关的信息，但不授予任何知识产权的许可证，也没有任何明示或暗示的保证，例如适用性、商业性或侵犯任何专利、版权或其他知识产权的权利。 3. Intel的产品在特定应用中设计时，并不是旨在也不会被设计为可能导致个人受伤或死亡的应用。Intel可以随时更改规格和产品描述，并不对由此引起的未来变化导致的冲突或不兼容性负责。 4. 当前已知的Intel®64架构处理器的设计缺陷或错误被称为errata。有关当前已识别的errata，可以请求获得信息。设计师在设计过程中不应依赖于未定义或保留的特征或指令。 5. 英特尔®超线程技术需要一个配备支持超线程技术的英特尔处理器、启用超线程技术的芯片组、BIOS和操作系统。性能将根据使用的具体硬件和软件而有所不同。 6. 在设计系统时应考虑使用支持超线程技术的英特尔处理器、启用超线程技术的芯片组、BIOS和操作系统来达到最佳性能。 7. Intel的产品信息是易变的，不应以这些信息作为最终设计的依据。在实际设计过程中，务必注意Intel可能随时会更改产品规格。 8. 设计师在使用扫描文档中的信息时，应考虑到OCR扫描技术可能存在的局限性，例如识别错误或漏识别个别字符，需要根据上下文理解并自行修正这些错误，以保证信息的连贯性和准确性。

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Intel® 64 and IA-32 Architectures

Software Developer’s Manual

Volume 2A:

Instruction Set Reference, A-M

NOTE: The Intel 64 and IA-32 Architectures Software Developer's Manual

consists of five volumes: Basic Architecture, Order Number 253665;

Instruction Set Reference A-M, Order Number 253666; Instruction Set

Reference N-Z, Order Number 253667; System Programming Guide,

Part 1, Order Number 253668; System Programming Guide, Part 2,

Order Number 253669. Refer to all five volumes when evaluating your

design needs.

Order Number: 253666-035US

June 2010

ii Vol. 2A

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE,

EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANT-

ED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH

PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED

WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES

RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY

PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.

UNLESS OTHERWISE AGREED IN WRITING BY INTEL, THE INTEL PRODUCTS ARE NOT DESIGNED NOR IN-

TENDED FOR ANY APPLICATION IN WHICH THE FAILURE OF THE INTEL PRODUCT COULD CREATE A SITUA-

TION WHERE PERSONAL INJURY OR DEATH MAY OCCUR.

Intel may make changes to specifications and product descriptions at any time, without notice. Designers

must not rely on the absence or characteristics of any features or instructions marked "reserved" or "unde-

fined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or

incompatibilities arising from future changes to them. The information here is subject to change without no-

tice. Do not finalize a design with this information.

The Intel

64 architecture processors may contain design defects or errors known as errata. Current char-

acterized errata are available on request.

Intel

Hyper-Threading Technology requires a computer system with an Intel

processor supporting Hyper-

Threading Technology and an Intel

HT Technology enabled chipset, BIOS and operating system.

Performance will vary depending on the specific hardware and software you use. For more information, see

http://www.intel.com/technology/hyperthread/index.htm; including details on which processors support Intel HT

Technology.

Intel

Virtualization Technology requires a computer system with an enabled Intel

processor, BIOS, virtual

machine monitor (VMM) and for some uses, certain platform software enabled for it. Functionality, perfor-

mance or other benefits will

vary depending on hardware and software configurations. Intel

Virtualization

Technology-enabled BIOS and VMM applications are currently in development.

64-bit computing on Intel architecture requires a computer system with a processor, chipset, BIOS, oper-

ating system, device drivers and applications enabled for Intel

64 architecture. Processors will not operate

(including 32-bit operation) without an Intel

64 architecture-enabled BIOS. Performance will vary de-

pending on your hardware and software configurations. Consult with your system vendor for more infor-

mation.

Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability

and a supporting operating system. Check with your PC manufacturer on whether your system delivers Ex-

ecute Disable Bit functionality.

Intel, Pentium, Intel Xeon, Intel NetBurst, Intel Core, Intel Core Solo, Intel Core Duo, Intel Core 2 Duo,

Intel Core 2 Extreme, Intel Pentium D, Itanium, Intel SpeedStep, MMX, Intel Atom, and VTune are trade-

marks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other coun-

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*Other names and brands may be claimed as the property of others.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing

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Copies of documents which have an ordering number and are referenced in this document, or other Intel

literature, may be obtained by calling 1-800-548-4725, or by visiting Intel’s website at http://www.intel.com

Vol. 2A iii

CONTENTS

PAGE

CHAPTER 1

ABOUT THIS MANUAL

1.1 IA-32 PROCESSORS COVERED IN THIS MANUAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

1.2 OVERVIEW OF VOLUME 2A AND 2B: INSTRUCTION SET REFERENCE . . . . . . . . . . . . . . . . . . 1-3

1.3 NOTATIONAL CONVENTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

1.3.1 Bit and Byte Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

1.3.2 Reserved Bits and Software Compatibility. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

1.3.3 Instruction Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

1.3.4 Hexadecimal and Binary Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

1.3.5 Segmented Addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

1.3.6 Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7

1.3.7 A New Syntax for CPUID, CR, and MSR Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7

1.4 RELATED LITERATURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8

CHAPTER 2

INSTRUCTION FORMAT

2.1 INSTRUCTION FORMAT FOR PROTECTED MODE, REAL-ADDRESS MODE, AND

VIRTUAL-8086 MODE 2-1

2.1.1 Instruction Prefixes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

2.1.2 Opcodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

2.1.3 ModR/M and SIB Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

2.1.4 Displacement and Immediate Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

2.1.5 Addressing-Mode Encoding of ModR/M and SIB Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

2.2 IA-32E MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

2.2.1 REX Prefixes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

2.2.1.1 Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

2.2.1.2 More on REX Prefix Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

2.2.1.3 Displacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13

2.2.1.4 Direct Memory-Offset MOVs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13

2.2.1.5 Immediates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14

2.2.1.6 RIP-Relative Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14

2.2.1.7 Default 64-Bit Operand Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15

2.2.2 Additional Encodings for Control and Debug Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15

CHAPTER 3

INSTRUCTION SET REFERENCE, A-M

3.1 INTERPRETING THE INSTRUCTION REFERENCE PAGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

3.1.1 Instruction Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

3.1.1.1 Opcode Column in the Instruction Summary Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

3.1.1.2 Instruction Column in the Opcode Summary Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

3.1.1.3 Operand Encoding Column in the Instruction Summary Table . . . . . . . . . . . . . . . . . . . 3-7

3.1.1.4 64-bit Mode Column in the Instruction Summary Table . . . . . . . . . . . . . . . . . . . . . . . . . 3-7

3.1.1.5 Compatibility/Legacy Mode Column in the Instruction Summary Table. . . . . . . . . . . 3-7

3.1.1.6 Description Column in the Instruction Summary Table. . . . . . . . . . . . . . . . . . . . . . . . . . 3-8

CONTENTS

Vol. 2A

PAGE

3.1.1.7 Description Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8

3.1.1.8 Operation Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8

3.1.1.9 Intel® C/C++ Compiler Intrinsics Equivalents Section . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12

3.1.1.10 Flags Affected Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15

3.1.1.11 FPU Flags Affected Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15

3.1.1.12 Protected Mode Exceptions Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15

3.1.1.13 Real-Address Mode Exceptions Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17

3.1.1.14 Virtual-8086 Mode Exceptions Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17

3.1.1.15 Floating-Point Exceptions Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17

3.1.1.16 SIMD Floating-Point Exceptions Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18

3.1.1.17 Compatibility Mode Exceptions Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18

3.1.1.18 64-Bit Mode Exceptions Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18

3.2 INSTRUCTIONS (A-M) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18

AAA—ASCII Adjust After Addition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19

AAD—ASCII Adjust AX Before Division. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21

AAM—ASCII Adjust AX After Multiply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23

AAS—ASCII Adjust AL After Subtraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25

ADC—Add with Carry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27

ADD—Add . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-31

ADDPD—Add Packed Double-Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . 3-34

ADDPS—Add Packed Single-Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . 3-37

ADDSD—Add Scalar Double-Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . 3-40

ADDSS—Add Scalar Single-Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . 3-43

ADDSUBPD—Packed Double-FP Add/Subtract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-46

ADDSUBPS—Packed Single-FP Add/Subtract. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-50

AESDEC—Perform One Round of an AES Decryption Flow . . . . . . . . . . . . . . . . . . . . . . . . 3-54

AESDECLAST—Perform Last Round of an AES Decryption Flow. . . . . . . . . . . . . . . . . . . 3-57

AESENC—Perform One Round of an AES Encryption Flow . . . . . . . . . . . . . . . . . . . . . . . . 3-60

AESENCLAST—Perform Last Round of an AES Encryption Flow . . . . . . . . . . . . . . . . . . . 3-63

AESIMC—Perform the AES InvMixColumn Transformation . . . . . . . . . . . . . . . . . . . . . . . . 3-66

AESKEYGENASSIST—AES Round Key Generation Assist . . . . . . . . . . . . . . . . . . . . . . . . . . 3-68

AND—Logical AND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-71

ANDPD—Bitwise Logical AND of Packed Double-Precision Floating-Point Values . . . 3-74

ANDPS—Bitwise Logical AND of Packed Single-Precision Floating-Point Values . . . . 3-76

ANDNPD—Bitwise Logical AND NOT of Packed Double-Precision Floating-Point Values. .

3-78

ANDNPS—Bitwise Logical AND NOT of Packed Single-Precision Floating-Point Values.3-

ARPL—Adjust RPL Field of Segment Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-82

BLENDPD — Blend Packed Double Precision Floating-Point Values . . . . . . . . . . . . . . . . 3-85

BLENDPS — Blend Packed Single Precision Floating-Point Values . . . . . . . . . . . . . . . . . 3-88

BLENDVPD — Variable Blend Packed Double Precision Floating-Point Values . . . . . . 3-91

BLENDVPS — Variable Blend Packed Single Precision Floating-Point Values . . . . . . . 3-94

BOUND—Check Array Index Against Bounds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-97

BSF—Bit Scan Forward . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-100

BSR—Bit Scan Reverse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-103

BSWAP—Byte Swap. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-106

Vol. 2A v

CONTENTS

PAGE

BT—Bit Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-108

BTC—Bit Test and Complement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-111

BTR—Bit Test and Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-114

BTS—Bit Test and Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-117

CALL—Call Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-120

CBW/CWDE/CDQE—Convert Byte to Word/Convert Word to Doubleword/Convert Dou-

bleword to Quadword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-139

CLC—Clear Carry Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-141

CLD—Clear Direction Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-142

CLFLUSH—Flush Cache Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-143

CLI — Clear Interrupt Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-145

CLTS—Clear Task-Switched Flag in CR0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-148

CMC—Complement Carry Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-150

CMOVcc—Conditional Move . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-151

CMP—Compare Two Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-158

CMPPD—Compare Packed Double-Precision Floating-Point Values . . . . . . . . . . . . . . . 3-161

CMPPS—Compare Packed Single-Precision Floating-Point Values . . . . . . . . . . . . . . . . 3-166

CMPS/CMPSB/CMPSW/CMPSD/CMPSQ—Compare String Operands . . . . . . . . . . . . . . . 3-171

CMPSD—Compare Scalar Double-Precision Floating-Point Values . . . . . . . . . . . . . . . . 3-177

CMPSS—Compare Scalar Single-Precision Floating-Point Values . . . . . . . . . . . . . . . . . 3-181

CMPXCHG—Compare and Exchange. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-185

CMPXCHG8B/CMPXCHG16B—Compare and Exchange Bytes . . . . . . . . . . . . . . . . . . . . 3-188

COMISD—Compare Scalar Ordered Double-Precision Floating-Point Values and Set

EFLAGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-191

COMISS—Compare Scalar Ordered Single-Precision Floating-Point Values and Set

EFLAGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-194

CPUID—CPU Identification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-197

CRC32 — Accumulate CRC32 Value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-232

CVTDQ2PD—Convert Packed Dword Integers to Packed Double-Precision FP Values . 3-

236

CVTDQ2PS—Convert Packed Dword Integers to Packed Single-Precision FP Values . . 3-

238

CVTPD2DQ—Convert Packed Double-Precision FP Values to Packed Dword Integers . 3-

241

CVTPD2PI—Convert Packed Double-Precision FP Values to Packed Dword Integers . . 3-

244

CVTPD2PS—Convert Packed Double-Precision FP Values to Packed Single-Precision FP

Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-247

CVTPI2PD—Convert Packed Dword Integers to Packed Double-Precision FP Values . . 3-

250

CVTPI2PS—Convert Packed Dword Integers to Packed Single-Precision FP Values . . . 3-

253

CVTPS2DQ—Convert Packed Single-Precision FP Values to Packed Dword Integers . . 3-

256

CVTPS2PD—Convert Packed Single-Precision FP Values to Packed Double-Precision FP

Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-259

CVTPS2PI—Convert Packed Single-Precision FP Values to Packed Dword Integers . . . 3-

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乐乐_J

2014-03-12

很好用，涉及了A-M的汇编指令集

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