MT8665
LTE SmartPlatform Application Processor
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Table 2-13. Constant tied pins ................................................................................................................... 62
Table 2-14. Baseband downlink specifications ......................................................................................... 65
Table 2-15. Baseband downlink specifications ..........................................................................................67
Table 2-16. LTE_BBTX specifications ....................................................................................................... 68
Table 2-17. C2K_BBTX specifications ....................................................................................................... 70
Table 2-18. ETDAC specifications .............................................................................................................. 71
Table 2-19. APC-DAC specifications ........................................................................................................... 72
Table 2-20. Definitions of AUXADC channels ........................................................................................... 73
Table 2-21. AUXADC specifications ...........................................................................................................74
Table 2-22. Clock squarer specifications .................................................................................................... 75
Table 2-23. ARMPLL specifications ........................................................................................................... 77
Table 2-24. MAINPLL specifications
........................................................................................................ 78
Table 2-25. MMPLL specifications ............................................................................................................ 78
Table 2-26. UNIVPLL specifications ......................................................................................................... 78
Table 2-27. MSDCPLL specifications .........................................................................................................79
Table 2-28. WPLL specifications ................................................................................................................79
Table 2-29. WHPLL specifications .............................................................................................................79
Table 2-30. C2KCPPLL specifications ....................................................................................................... 80
Table 2-31. C2KDSPPLL specifications ..................................................................................................... 80
Table 2-32. CR4PLL specifications ............................................................................................................ 80
Table 2-33. VENCPLL specifications ......................................................................................................... 81
Table 2-34. TVDPLL specifications ............................................................................................................ 81
Table 2-35. LTEDSPPLL specifications ................................................................................................
...... 81
Table 2-36. APLL1 specifications ............................................................................................................... 82
Table 2-37. Temperature sensor specifications ........................................................................................ 82
Table 2-38. Thermal operating specifications .......................................................................................... 84
Figure 1-1. High-level MT8665 functional block diagram .......................................................................... 7
Figure 1-2. Block diagram of MT8665 Product Description ..................................................................... 16
Figure 2-1. Ball map view for LPDDR3 ...................................................................................................... 17
Figure 2-2. Ball map view for LPDDR2 ...................................................................................................... 18
Figure 2-3. IO types in state of pins ........................................................................................................... 37
Figure 2-4. Basic timing parameter for LPDDR3 commands ................................................................... 55
Figure 2-5. Basic timing parameter for LPDDR3 write ............................................................................. 55
Figure 2-6. Basic LPDDR3 read timing parameter .................................................................................. 56
Figure 2-7. Basic timing parameter for LPDDR2 commands .................................................................. 58
Figure 2-8. Basic timing parameter for LPDDR2 write ........................................................................... 59
Figure 2-9. Basic timing parameter for LPDDR2 read ............................................................................. 59
Figure 2-10. Block diagram of LTE_BBRX-ADC ...................................................................................... 65
Figure 2-11. Block diagram of C2K_BBRX-ADC .......................................................................................67
Figure 2-12. Block diagram of LTE_BBTX ............................................................................................... 68
Figure 2-13. Block diagram of C2K_BBTX ............................................................................................... 70
Figure 2-14. Block diagram of ETDAC ....................................................................................................... 71
Figure 2-15. Block diagram of APC-DAC (same architecture for two APC-DACs) .................................. 72
Figure 2-16. Block diagram of AUXADC .................................................................................................... 73
Figure 2-17. Block diagram of ARMPLL .....................................................................................................76
Figure
2-18. Block diagram of PLLGP ........................................................................................................ 77
Figure 2-19. Outlines and dimensions of VFBGA 12.6mm*12.6mm, 641 balls, 0.4mm pitch package 84
Figure 2-20. Top mark of MT8665 ............................................................................................................ 85
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2018-10-15
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hank_fan2020-12-11官方MT8665资料，2016年的，有点老，谢谢分享。
blackmash2018-10-16pdf打开一直报错，里面除了标题，没有内容？
