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loginid=yszzw118@droi.com,time=2016-03-29 23:49:23,ip=124.74.128.198,doctitle=MT6750 LTE-A Smartphone Application Processor Functional Specification V1.3.pdf,company=DROI_WCX

This document contains information that is proprietary to MediaTek Inc.

Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.

Version: 1.3

Release date: 2016-02-15

Specifications are subject to change without notice.

MT6750 LTE-A Smartphone Application

Processor Functional Specification

loginid=yszzw118@droi.com,time=2016-03-29 23:49:23,ip=124.74.128.198,doctitle=MT6750 LTE-A Smartphone Application Processor Functional Specification V1.3.pdf,company=DROI_WCX

MT6750

LTE-A Smartphone Application Processor

Functional Specification

Confidential A

Page 3 of 225

This document contains information that is proprietary to MediaTek Inc.

Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.

Table of Contents

Document Revision History ............................................................................................. 2

Table of Contents .............................................................................................................. 3

Preface ........................................................................................................................... 10

1 System Overview ..................................................................................................... 11

1.1 Highlighted Features Integrated in MT6750.......................................................................... 11

1.2 Platform Features ..................................................................................................................... 13

1.3 Modem Features ...................................................................................................................... 15

1.4 Connectivity Features .............................................................................................................. 17

1.5 Multimedia Features ................................................................................................................ 19

1.6 General Description ................................................................................................................. 21

2 Product Description ............................................................................................... 23

2.1 Pin Description ........................................................................................................................ 23

2.2 Electrical Characteristic .......................................................................................................... 40

2.3 System Configuration .............................................................................................................. 61

2.4 Power-on Sequence ................................................................................................................. 62

2.5 Analog Baseband ..................................................................................................................... 63

2.6 Package Information ................................................................................................................ 72

2.7 Power Delivery Network .......................................................................................................... 74

2.8 Ordering Information .............................................................................................................. 75

3 MCU and Bus Fabric .............................................................................................. 76

3.1 MCU System ............................................................................................................................. 76

3.2 On-chip Memory Controller ................................................................................................... 85

3.3 External Interrupt Controller ................................................................................................. 88

3.4 System Interrupt Controller .................................................................................................... 91

3.5 Infrastructure System Configuration Module ....................................................................... 95

3.6 External Memory Interface ..................................................................................................... 97

3.7 DRAM Controller .................................................................................................................... 99

3.8 AP_DMA .................................................................................................................................104

3.9 CQ_DMA ................................................................................................................................109

4 Clock and Power Control ...................................................................................... 111

4.1 Top Clock Generator ............................................................................................................... 111

4.2 Top Reset Generator Unit ...................................................................................................... 117

4.3 PMIC Wrapper .......................................................................................................................120

4.4 Frequency Hopping Controller ............................................................................................. 122

5 Peripherals .......................................................................................................... 123

5.1 Pericfg Controller ................................................................................................................... 123

5.2 GPIO Control .......................................................................................................................... 125

5.3 Keypad Scanner ...................................................................................................................... 132

5.4 UART ...................................................................................................................................... 136

5.5 USB ......................................................................................................................................... 139

5.6 USB 2.0 High Speed Dual-Role Controller ........................................................................... 142

5.7 USBPHY Register File ............................................................................................................ 147

loginid=yszzw118@droi.com,time=2016-03-29 23:49:23,ip=124.74.128.198,doctitle=MT6750 LTE-A Smartphone Application Processor Functional Specification V1.3.pdf,company=DROI_WCX

MT6750

LTE-A Smartphone Application Processor

Functional Specification

Confidential A

Page 4 of 225

This document contains information that is proprietary to MediaTek Inc.

Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.

5.8 SPI Interface Controller ......................................................................................................... 150

5.9 Memory Stick and SD card Controller .................................................................................. 154

5.10 AUXADC .................................................................................................................................160

5.11 I2C/SCCB Controller ............................................................................................................. 163

5.12 Pulse-Width Modulation (PWM) .......................................................................................... 168

5.13 General-Purpose Timer (GPT) .............................................................................................. 170

5.14 Thermal Controller ................................................................................................................ 172

5.15 IRTX ........................................................................................................................................ 179

5.16 Audio System .......................................................................................................................... 183

5.17 BTIF ........................................................................................................................................ 186

6 Multimedia .......................................................................................................... 189

6.1 Display Controller .................................................................................................................. 189

6.2 CAM ........................................................................................................................................ 191

6.3 SENINF_TOP (Sensor Interface).......................................................................................... 192

6.4 FDVT ....................................................................................................................................... 193

6.5 DISPLAY PWM Generator.................................................................................................... 200

6.6 DPI (Digital Parallel Interface) .............................................................................................201

6.7 Display Serial Interface ......................................................................................................... 202

6.8 JPEG Encoder ....................................................................................................................... 203

6.9 JPEG Decoder ....................................................................................................................... 206

6.10 Video Decoder ........................................................................................................................ 211

6.11 H.264 Video Encoder ............................................................................................................. 219

6.12 MFG ........................................................................................................................................ 221

7 Analog Baseband.................................................................................................. 223

7.1 AP Mixedsys .......................................................................................................................... 223

loginid=yszzw118@droi.com,time=2016-03-29 23:49:23,ip=124.74.128.198,doctitle=MT6750 LTE-A Smartphone Application Processor Functional Specification V1.3.pdf,company=DROI_WCX

MT6750

LTE-A Smartphone Application Processor

Functional Specification

Confidential A

Page 5 of 225

This document contains information that is proprietary to MediaTek Inc.

Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.

Lists of Figures

Figure 1-1. High-level MT6750 functional block diagram ......................................................................... 12

Figure 1-2. Block diagram of MT6750 ........................................................................................................ 21

Figure 1-3. Bus structure of MT6750 ......................................................................................................... 22

Figure 2-1. Ball map view ........................................................................................................................... 23

Figure 2-2. Basic timing parameter for LPDDR3 commands .................................................................. 45

Figure 2-3. Basic timing parameter for LPDDR3 write ............................................................................ 46

Figure 2-4. Basic LPDDR3 read timing parameter .................................................................................. 46

Figure 2-5. SPI timing diagram ................................................................................................................. 48

Figure 2-6. I2S master mode timing diagram ........................................................................................... 49

Figure 2-7. I2C timing diagram of standard mode (100kHz) and fast mode (400kHz) ........................ 50

Figure 2-8. MSDC input timing diagram of default speed ........................................................................ 51

Figure 2-9. MSDC output timing diagram of default speed ...................................................................... 51

Figure 2-10. MSDC input timing diagram of high speed ......................................................................... 52

Figure 2-11. MSDC output timing diagram of high speed ........................................................................ 52

Figure 2-12. MSDC clock timing diagram of SDR12/SDR25/SDR50/SDR104 mode ............................ 53

Figure 2-13. MSDC input timing diagram of SDR50/SDR104 mode ...................................................... 53

Figure 2-14. MSDC output timing diagram of fixed data window (SDR12/SDR25/SDR50) ................ 54

Figure 2-15. MSDC output timing diagram of variable window (SDR104) ............................................. 54

Figure 2-16. MSDC clock timing diagram of DDR50 speed mode. .......................................................... 55

Figure 2-17. MSDC input/output timing diagram of DDR50 speed mode .............................................. 55

Figure 2-18. MSDC clock timing diagram of HS200 ................................................................................ 56

Figure 2-19. MSDC input timing diagram of HS200................................................................................ 56

Figure 2-20. MSDC output timing diagram of HS200 .............................................................................. 57

Figure 2-21. MSDC input timing diagram of HS400 ................................................................................ 58

Figure 2-22. MSDC output timing diagram of HS400 ............................................................................. 58

Figure 2-23. Power on sequence ................................................................................................................ 62

Figure 2-24. Block diagram of BBRX-ADC ............................................................................................... 64

Figure 2-25. Block diagram of BBTX ......................................................................................................... 65

Figure 2-26. Block diagram of ETDAC ...................................................................................................... 66

Figure 2-27. Block diagram of DETADC ....................................................................................................67

Figure 2-28. Block diagram of APC-DAC .................................................................................................. 68

Figure 2-29. Outlines and dimensions of TFBGA 13mm*13.4mm, 873-ball, 0.4mm pitch package ..... 72

Figure 2-30. Top marking of MT6750 ........................................................................................................ 75

Figure 3-1. Block diagram of on-chip memory controller ........................................................................ 85

Figure 3-2. Security memory protection scheme ...................................................................................... 86

Figure 3-3. Block diagram of external interrupt controller ..................................................................... 88

Figure 3-4. System level block diagram of system interrupt controller ................................................... 91

Figure 3-5. Block diagram of system interrupt controller ........................................................................ 92

Figure 3-6. DCM in action .......................................................................................................................... 95

Figure 3-7. EMI/DRAM controller top connection .................................................................................. 98

Figure 3-8. Block diagram of DRAM controller ...................................................................................... 102

Figure 3-9. APDMA block diagram .......................................................................................................... 105

Figure 4-1. Block diagram of clock architecture ....................................................................................... 111

Figure 4-2. Example of clock multiplier ................................................................................................... 112

Figure 4-3. PLL block diagram ................................................................................................................. 113

Figure 4-4. TOPCKGEN FMETER structure ........................................................................................... 115

Figure 4-5. Block diagram of top reset generation unit .......................................................................... 117