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Lattice Confidential
REVEAL INTRODUCTION
FPGA ON-CHIP DEBUG
Lattice Diamond Reveal © 2010 Lattice Semiconductor CorporationPage: 2
Reveal Training
Agenda
•
Highlights
•
User Tool Flow
•
Key Concepts
•
Tool Details
•
Summary
•
JTAG Builder Flow
Lattice Diamond Reveal © 2010 Lattice Semiconductor CorporationPage: 3
Reveal Most Important to Remember!
•
Reveal Users Guide
–
PDF (176 pages) available in
on-line help and website
–
Complete information about
all Reveal features
•
Reveal Troubleshooting
Guide
–
PDF (9 pages) available in on-
line help and website
–
Complete information about
all Reveal features
•
Look There First!
–
Rare problem not covered in
these documents
Lattice Diamond Reveal © 2010 Lattice Semiconductor CorporationPage: 4
Reveal Introduction
•
Hardware Debugging Tool
–
Embedded Logic Analyzer for debugging internal signals
–
Supports MachXO, EC/ECP, XP, ECP2/M, XP2, SC/M, ECP3 devices
–
Many advanced features compared to ispTRACY
Lattice Diamond Reveal © 2010 Lattice Semiconductor CorporationPage: 5
Reveal Highlights
•
Project Navigator Integration
–
Reveal “rvl” file indicates presence of debug
–
Original design can be updated and debug automatically reapplied
–
Debug can be removed by deleting “rvl” file from Project
Navigator
•
Uses Signal-Centric Method
–
Eliminates user need to “design” and connect debug cores
–
Significantly improved ease of use
•
Advanced Triggering Capabilities
–
Trigger Units (TU) for dynamic signal comparisons
–
Trigger Expressions (TE) for dynamic combinations and
sequences of trigger units
–
Most advanced triggering capabilities of any on-chip debug tool
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- WHL20112014-08-30FAE的资料还是不错的
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